JPS6454818A - Offset compensation circuit - Google Patents

Offset compensation circuit

Info

Publication number
JPS6454818A
JPS6454818A JP21014487A JP21014487A JPS6454818A JP S6454818 A JPS6454818 A JP S6454818A JP 21014487 A JP21014487 A JP 21014487A JP 21014487 A JP21014487 A JP 21014487A JP S6454818 A JPS6454818 A JP S6454818A
Authority
JP
Japan
Prior art keywords
offset compensation
time
signal
correct
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21014487A
Other languages
Japanese (ja)
Other versions
JPH0783266B2 (en
Inventor
Masami Tsuchida
Yoshimi Iso
Takao Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Pioneer Corp
Original Assignee
Hitachi Ltd
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Pioneer Electronic Corp filed Critical Hitachi Ltd
Priority to JP62210144A priority Critical patent/JPH0783266B2/en
Priority to US07/234,874 priority patent/US4965867A/en
Publication of JPS6454818A publication Critical patent/JPS6454818A/en
Publication of JPH0783266B2 publication Critical patent/JPH0783266B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To accurately perform offset compensation even at a time when an input signal is impressed, by storing the value of a correct offset compensation voltage at the time of inputting no signal in a memory means, and performing the offset compensation based on the correct offset compensation voltage at the time of impressing the input signal. CONSTITUTION:At the time of inputting no signal, a switching means 6 is connected to contact (a) side, and the correct compensation voltage obtained from an integrator 3 is fed back via a filter 4, and the offset compensation is applied on a circuit system, and simultaneously, an offset correction voltage is supplied to the memory means 5, and stored in the means. At the time of impressing the input signal, the switching means 6 is switched to contact (b) side, and the correct offset compensation voltage at the time of inputting no signal stored in the memory means 5 is fed back via the filter 4, then, the offset compensation is applied on the circuit system. In such a way, it is possible to perform the offset compensation always based on the correct offset compensation voltage even at the time of impressing the input signal such as a music signal, etc.
JP62210144A 1987-08-20 1987-08-26 Offset compensation circuit Expired - Lifetime JPH0783266B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62210144A JPH0783266B2 (en) 1987-08-26 1987-08-26 Offset compensation circuit
US07/234,874 US4965867A (en) 1987-08-20 1988-08-22 Offset compensation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62210144A JPH0783266B2 (en) 1987-08-26 1987-08-26 Offset compensation circuit

Publications (2)

Publication Number Publication Date
JPS6454818A true JPS6454818A (en) 1989-03-02
JPH0783266B2 JPH0783266B2 (en) 1995-09-06

Family

ID=16584499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62210144A Expired - Lifetime JPH0783266B2 (en) 1987-08-20 1987-08-26 Offset compensation circuit

Country Status (1)

Country Link
JP (1) JPH0783266B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1141130A (en) * 1997-07-22 1999-02-12 Oki Electric Ind Co Ltd Mixer circuit and receiver
JP2007259132A (en) * 2006-03-23 2007-10-04 Matsushita Electric Works Ltd Receiving apparatus
JP2012165161A (en) * 2011-02-07 2012-08-30 Rb Controls Co Device with remote control

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730417A (en) * 1980-07-30 1982-02-18 Hitachi Ltd Analog-to-digital converter
JPS61274454A (en) * 1985-05-29 1986-12-04 Nippon Telegr & Teleph Corp <Ntt> Dc drift compensating circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730417A (en) * 1980-07-30 1982-02-18 Hitachi Ltd Analog-to-digital converter
JPS61274454A (en) * 1985-05-29 1986-12-04 Nippon Telegr & Teleph Corp <Ntt> Dc drift compensating circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1141130A (en) * 1997-07-22 1999-02-12 Oki Electric Ind Co Ltd Mixer circuit and receiver
JP2007259132A (en) * 2006-03-23 2007-10-04 Matsushita Electric Works Ltd Receiving apparatus
JP2012165161A (en) * 2011-02-07 2012-08-30 Rb Controls Co Device with remote control

Also Published As

Publication number Publication date
JPH0783266B2 (en) 1995-09-06

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