JPS61274454A - Dc drift compensating circuit - Google Patents

Abstract

PURPOSE:To increase the noise margin in a multivalued signal identification apparatus with effectively adjusting DC offset by using a reversible counter in place of an analog integrating circuit and adding a fixed value to a full adder in an asynchronizing time. CONSTITUTION:An octenary signal is inputted from an input terminal 1 and the output of an A/D converter 3 is inputted to a reversible counter 10 of eight stages which is prepared to integrate a high-order fourth bit in its output through a full adder 9. In a synchronizing state, so that '1' is inputted to a monitor terminal 11, the reversible counter 10 is counted down when the value of the high-order fourth bit is '1', meanwhile, when it is '0', the counter 10 is operated to count up. On the other hand, in an asynchronizing state, so that the signal of '0' is inputted to an asynchronous detecting monitor 11, the input of a clock to the counter is terminated and the operation of the counter is actually terminated and therefore, the data just before the asynchronizing time is added to the full adder 9 as a fixed data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit configuration method for compensating for DC drift F on the demodulation side in a digital communication system.

[Conventional technology]

FIG. 1 is a diagram showing the input/output relationship when an 8-level amplitude signal is identified by an A/D converter. Referring to the figure, the DC drift F and its compensation will be explained using an 8 (=23) value signal as an example.

In Figure 1, the most significant bit uses the center level of the 8-value signal as the identification level (hereinafter referred to as path 1 identification).
, Also, the top 2 Bi? Tome further sets half the amplitude of path 2 as the identification level (hereinafter referred to as path 2 identification), and furthermore sets the upper third bit to half the amplitude as the identification level (hereinafter referred to as path 3 identification). , top 4
The 8-value signal point of the second bit is used as the identification level, and the information represents the direction of code amount interference or identification error (hereinafter referred to as path 4 identification).

In a system scrambled on the transmitting side, in the case of an 8-level signal, the existence certainty of 0'' and 1'' is 50% when identifying paths 1 and 4, but for example, as shown in Figure 2 b), If the signal point is slightly shifted upward, all information on path 4 becomes 1
” Therefore, control is performed to lower the DC level.

Furthermore, in a pseudo-stable state as shown in FIG. 2(b), the probability of existence of 1'' in path 1 increases at a ratio of 5 to 3, so control is performed to lower the DC level.

In this way, the signal placement was incorrect due to DC/INOR/F, etc. (
In the case of deviation), the DC offset has conventionally been controlled by a circuit having a configuration as shown in FIG.

In FIG. 3, an 8-level signal is input to the input terminal 1, passed through a DC amplifier 2 capable of changing the amount of DC offset, and then passed through an A/D converter 3 to identify the signal.
Enter. The A/D converter 3 performs identification using a timing signal from a terminal 4.

Next, a control signal is obtained by passing through a resistor 5.6 for adding the output signals of path 1 and path 4, and passing through a low-pass filter 7 for integrating the added output. By feeding back the signal to the DC amplifier 2 and controlling the amount of DC offset, it is configured to prevent reduction in noise margin due to DC offset.

[Problem that the invention seeks to solve]

As mentioned above, conventional DC drift compensation circuits require a DC amplifier that can change the amount of offset, and because they are controlled using analog signals, subtle changes in control loop gain and loop time constant are required. There was a problem in that it required adjustment.

The present invention provides a DC drift F compensation circuit that can effectively increase the DC offset amount and increase the noise margin of a multilevel signal discriminator without making fine adjustments to the circuit such as adjusting the offset of a DC amplifier. The purpose is to

[Means for solving problems]

The present invention achieves the above object by the means described in the claims, and is a circuit for compensating for DC drift in a digital communication system.
The present invention uses a reversible counter to correspond to the analog integration circuit using R, and whereas conventionally a DC amplifier that can change the DC offset amount was used, the present invention uses a reversible counter. In this case, this is replaced with a fixed DC amplifier and a full adder. The present invention is also different from the conventional technology in that it detects synchronization and asynchrony, performs normal control when synchronized, and adds a fixed value to the full adder in order to prevent adverse effects on the main signal system when non-synchronized.

〔Example〕

FIG. 4 is a block diagram of the first embodiment of the present invention, and corresponds to claim (1).

To explain using an 8-value (=23) signal as an example using Figure 1, the 8-value signal is input from input terminal 1, and extracted from the received signal by A/D converter 3, which has an 8-bit output. The timing signal (input from terminal 4) is used to identify the signal. Among the 8 bits, the upper 3 bits are demodulated data (pass 1 to pass 3 in Figure 1), and
An 8-stage reversible counter 1 for passing the output of the A/D converter 3 through a full adder 9 and integrating the fourth most significant bit of the output.
Enter 0.

Here, the upper 4th bit indicates the direction of code amount interference, and when it is '1', the direction of the DC code is positive;
Further, it is assumed that when the value is '0'', the direction of the DC dot I77 is in the negative direction.

In the synchronous state, "1" is input to the monitor terminal 11, so a clock signal is input to the counter as shown in FIG. while counting down '0''
At this time, the reversible counter 10 operates to count up. For example, the upper 6 bits of the output of the reversible counter are input to the full adder 9, and the initial value of the counter is =o
o o o o o o o", if the value "1" of the upper 4th bit is input to the reversible counter, its output will count down and become "111111"
(In this case, carry or borrow caused by the operation is ignored.) If this value is added to the full adder, the 8-bit A/
The D converter output and the 6-bit counter output are added so that the LSBs match, so for example, when the A/D converter output is "10011001", the output is '10011001'.
+ becomes “XX111111” (× is arbitrary), and the least significant bit is reduced by 1, resulting in “xxotiooo”
Therefore, it is possible to shift to the negative side by the least significant bit and return the offset to normal.

In the above example, the counter has the upper 6 bits of input.
The output of the counter uses bits and the input clock is 4.
Since it changes bit by bit, subtraction is 174 bits of the identification clock.
is carried out at a speed of

When the upper 4th bit is "0" m, the situation is completely opposite to the above example, and it is possible to shift the offset to the positive side by the amount that was shifted to the negative side and return the offset to normal.

On the other hand, in the case of asynchronous, a "0" signal is input to the asynchronous detection monitor 11, so the clock input to the counter stops.
Since the operation of the counter effectively stops, the data immediately before the asynchronous operation is added to the full adder as fixed data.

Therefore, during synchronization, normal control is performed, and during non-synchronization, the data immediately before non-synchronization is added to the full adder as fixed data so as not to adversely affect the main signal. The offset compensation accuracy improves as the number of output bits of the A/D converter, the number of stages of the reversible counter, and the number of bits of the full adder increase.

FIG. 5 is a block diagram showing a second embodiment of the present invention, and corresponds to claim (2).

The state in Figure 2 mentioned above! ! In the case of a pseudo-stable state as shown in l (b), it becomes difficult to control the offset correctly using the information in the upper 4th bit. Therefore, in such a case, control can be performed by using the most significant bit of the A/D converter output. Also, state 1 in this diagram and final circuit 2! Returning to (a), control becomes possible using the information of the upper 4th bit.

In this embodiment, during synchronization, a reversible counter 13 is used to integrate the most significant bit, a full adder 12 is used to add its output and the A/D converter output, and a reversible counter 10 is used to integrate the fourth most significant bit. and its output and full adder 12
The offset is compensated for by a full adder 9 that adds the outputs of .

As for the two full adders, each of them requires a high-speed full adder that operates at a speed equivalent to the code speed. In addition, at the time of non-synchronization, the aO input to the asynchronous detection monitor 11
'', the clocks of the counters 10 and 13 are stopped and the data immediately before asynchronous is generated as fixed data, 1. This is done so as not to adversely affect the main signal.

FIG. 6 is a block diagram of a third embodiment of the present invention,
This figure shows a circuit configuration for saving one high-speed full adder in the embodiment shown in FIG. 5 above. That is, the most significant bit and the fourth most significant bit are integrated separately by independent reversible counters 10 and 13, and the outputs are added to the full adder 14, and the output is added to the A/D converter output. Total addition! #9 represents an offset compensation circuit. Since the number of output bits of the counter is less than the number of stages, if the difference is P, the data rate of the counter output is 1/2P of the input clock, so the sixth
Figure #! All the mg units 14 in the system need only be operated at low speed, and only one high-speed full adder is required to operate at a speed equivalent to the code speed.

FIG. 7 is a block diagram showing an example of an 8-stage reversible counter configuration. In this case, the upper 6 bits of the 8 stages are taken out as output bits.

In FIG. 7, the clock signal is input to the terminal 15, the synchronous/asynchronous detection signal is input to the motor terminal 11, and the AND circuit 25
controls on/off of the counter. In addition, the control information for the 7th pump is input to the input terminal 16.
Output is obtained from the Q terminal through the 0 knobs 17 to 24.

In the figure, in addition to the above, 26 represents an AND circuit, 27 represents an OR circuit, and 28 represents an inversion circuit.

〔Effect of the invention〕

As explained above, the DC drift compensation circuit according to the present invention, which has a synchronous/asynchronous detection function, detects the DC offset of the input analog signal of the A/D converter using a digital signal after A/D conversion. This has the advantage that it can be realized without any adjustment and that it can provide a circuit configuration suitable for LSI integration.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the input/output relationship when an 8-level amplitude signal is identified by an A/D converter, Fig. 2 is a diagram showing an example of the state when the DC level of the amplitude signal fluctuates, and Fig. 3 is a block diagram showing an example of a conventional DC offset control circuit,
FIG. 4 is a block diagram showing the first embodiment of the present invention, and FIG.
The figure shows the second embodiment of the present invention, FIG. 6 is a block diagram showing the #I3 embodiment of the present invention, and FIG. 7 shows the 8p! 1072 is a diagram illustrating an example of a configuration of nine reversible forces; FIG. 1...Input terminal, 2...DC amplifier, 3...A/D converter, 4...
・ Timing signal terminal, 5.6...Resistor 1.7...Low pass filter, 8...
...Fixed DC amplifier, 9.12 ...Full adder, 10.13 ...Reversible counter,
11... Monitor terminal, 14...
Low speed omniscient ttn, 15... Clock signal input terminal, 16... Up/down control signal input terminal, 17-24... T7 rip 70 flip,
25.26 ・・・・・・AND circuit, 27 ・・・
...Disjunctive circuit, 28 ...Inverting circuit agent Patent attorney Book m * No. 1 Illustration 1rj Poem Condition (d) Condition (b) $2 Figure 3 Figure 4

Claims (2)

[Claims] (1) An A/D converter that receives a scrambled 2^N-value (N is an integer) multi-value amplitude signal on the transmitting side and outputs a J (J≧N+1)-bit signal; It consists of a full adder that receives the output of the A/D converter as input, and M stages (M is an integer of 2 or more) for integrating the output of the upper N+1 bit of the full adder, and system synchronization.・
and a reversible counter having a signal input terminal for monitoring asynchronization, and the upper K of the output of the reversible counter (K is K≦M
) bit to a full adder, and when asynchronous, data immediately before becoming asynchronous is input to the full adder as fixed data. (2) An A/D converter that receives a scrambled 2^N multi-value amplitude signal on the transmitting side and outputs a J (J≧N+1) bit signal, and the A/D converter. A first full adder that receives the output of the first full adder as an input, a second full adder that receives the output of the first full adder as an input, and integrates the most significant bit output of the second full adder. A first reversible counter consisting of M stages (M is an integer of 2 or more) and having a signal input terminal for monitoring synchronization/asynchronousness of the system and the upper N+1 bit output of the second adder are integrated. and a second reversible counter consisting of M stages and having a signal input terminal for monitoring system synchronization/asynchronousness. In addition to inputting to the first full adder, the upper K bits of the output of the second reversible counter are also input to the second full adder, while when asynchronous, the first full adder and the second full adder A DC drift compensation circuit characterized in that data immediately before becoming asynchronous is input to the device as fixed data.