JPH0758798A - Demodulator - Google Patents

Abstract

PURPOSE:To provide a demodulator for preventing the malfunction of a DC offset control circuit due to rader pulse interference relating to the demodulator used for digital radio communications provided with the DC offset control circuit for compensating signal point distortion generated in a transmission side modulation circuit and the DC component drift of a demodulation circuit. CONSTITUTION:A rader pulse detection circuit 30 generates rader pulse detection signals and outputs them to a control signal generation circuit 20 at the time of detecting rader pulses based on digital demodulation signals from an A/D converter 13. The control signal generation circuit 20 outputs '0' for fixing DC offset other than '1' for performing offset control in a positive direction and '-1' for performing DC offset control in a negative direction as DC offset detection signals and outputs '0' only when the rader pulse detection signals are inputted. Thus, during rader pulse duration, a correct value is held for the value of DC offset control signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation device, and more particularly to a digital radio communication provided with a DC offset control circuit for compensating for a signal point distortion generated in a transmission side modulation circuit and a DC component drift of the demodulation circuit. The present invention relates to a demodulator used.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an example of a demodulator used for digital radio communication provided with a conventional DC offset control circuit. This demodulator is used in a two-phase phase modulation system or a multilevel quadrature modulation system, but for simplicity, the case of the two-phase phase modulation system will be described.

The intermediate frequency (IF) signal input to the terminal 10 is supplied to the demodulation circuit 11, where it is demodulated into a baseband demodulation signal. This baseband demodulated signal is supplied to the direct current (DC) offset control circuit 12, and is DC by the DC offset control signal from the integration circuit 15 described later.
After being offset controlled, it is supplied to the A / D converter 13.

The A / D converter 13 performs analog-to-digital conversion on the input signal to generate a digital demodulation signal, which is output to the terminal 16 and supplied to the control signal generation circuit 14. The control signal generation circuit 14 generates an offset detection signal based on this input digital demodulation signal and outputs it to the integration circuit 15. The integrating circuit 15 smoothes the input offset detection signal and outputs it to the DC offset control circuit 12 as a DC offset control signal.

Next, the DC offset control operation will be described with reference to FIG. FIG. 8 shows A / D conversion values and signal points of the digital demodulated signal. The path 1 signal indicates a transmission signal, and the path 2 signal indicates a deviation from the specified value of the reception signal. Therefore, the path 1 signal and the path 2 signal are called a determination signal and an error signal, respectively. When the digital demodulated signal is correctly converged to the specified value (signal point 1 in FIG. 8), the following four cases of combinations of the path 1 signal and the path 2 signal equally occur.

(1,1), (1,0), (0,1),
(0,0) However, for example, the input level is DC in the positive direction.
When offset, the signal point is always above the specified value (Fig. 8).
, And the combination of the path 1 signal and the bus 2 signal can be either (1, 1) or (0, 1). On the contrary, when the input level is DC offset in the negative direction, the signal point is always below the specified value (see FIG. 8).
Signal point 3), and the combination of the path 1 signal and the bus 2 signal can be either (1,0) or (0,0).

That is, the path 2 signal (error signal) indicates the DC offset direction of the signal point, and when the error signal is "1", the signal point indicates the upward DC offset of the specified value and "0". In the case of, it means that the signal point has a DC offset below the specified value.

Based on this error signal, the control signal generation circuit 14 outputs "-1" for controlling the DC offset in the negative direction when the error signal is "1" based on this error signal, and the error signal is "0". In the case of, the integrating circuit 1 uses “1” for DC offset control in the positive direction as a DC offset detection signal.
Output to 5. The integrating circuit 15 smoothes this DC offset detection signal input for each symbol and sends the DC offset control signal to the DC offset control circuit 12.

The above is the case of the DC offset control in the case of the two-phase phase modulation system, but in the case of the quadrature modulation system,
The DC offset control can be performed in the same manner as described above by expanding the DC offset control into two dimensions, the in-phase side and the quadrature side. Further, in the case of the multilevel quadrature modulation method, the error signal is not the path 2 but the path corresponding to the modulation method (ie,
In the case of QAM of 4 ^m value (m ≧ 2), the path may be m + 1).

According to the demodulator having such a configuration, it is possible to compensate the signal point distortion and the DC drift of the demodulator circuit which occur in the transmitter modulation circuit in the digital radio communication system.

[0011]

However, when the above digital radio communication system is used at sea or in coastal areas, pulse-like radar interference (hereinafter referred to as radar pulse interference) generated by a ship radar or the like. ) Exists, this radar pulse interference becomes a large level instantaneously, and a stepwise level fluctuation that disappears instantaneously occurs periodically, and sometimes it becomes a level equivalent to the target signal. Not only a bit error may occur in the target signal during the pulse duration, but also a malfunction of the DC offset control circuit 12 of the demodulator may be induced.

To further explain the situation of this malfunction, when the carrier frequency of radar pulse interference superimposed on the target signal is a value near the carrier frequency of the target signal, the baseband demodulated signal output from the demodulation circuit is An interference signal having a frequency component near DC is included. This interference signal gives a DC offset corresponding to the amplitude of the interference signal to the amplitude of the target signal, and as a result, the signal point of the received signal is in a pseudo DC offset state.

The DC offset control circuit 12 of the conventional demodulator reacts to this pseudo DC offset state, and the time during which radar pulse interference occurs is pseudo D.
Wrong control is applied in the direction of compensating for the C offset. If the radar pulse interference is interrupted in this state, the DC offset control circuit 12 in the malfunction state will perform DC offset control in the opposite direction of the DC offset due to the interference signal, although there is no interference signal this time.

For example, assuming that the interference signal contained in the demodulated baseband signal is generated in the positive direction during the period as shown in FIG. 9A, the output signal of the DC offset control circuit 12 is as shown in FIG. As shown in (B), the offset control is performed in the direction for compensating for the pseudo offset during the above period, and in the period immediately after the radar pulse interference is interrupted, D in the reverse direction due to the DC offset control malfunction is generated.
Offset control is applied in the direction of compensating for the C offset.

That is, if the DC offset control is performed in the conventional manner, not only the period in which the radar pulse interference is occurring, but the offset malfunction occurs for a while even if the radar pulse interference is interrupted. In the state where the DC offset is shifted, the interval between the signal point and the threshold value is narrowed, so that the bit error rate characteristic is deteriorated. In particular, the multi-level modulation method has a greater influence on the bit error rate characteristic.

As described above, in the digital radio communication system, in the conventional demodulation device having the offset control circuit for compensating for the signal point distortion generated in the transmission side modulation circuit and the DC drift of the demodulation circuit, the occurrence of radar pulse interference causes There is a drawback that bit errors are likely to occur not only in the duration of radar pulse interference but also in the duration of radar pulse interference. Further, various offset control circuits themselves have been conventionally known (for example, JP-A-63-16).
No. 0404, JP-A-64-81417, etc.) does not exist to eliminate the above defects.

The present invention has been made in view of the above points,
An object of the present invention is to provide a demodulation device that prevents a malfunction of a DC offset control circuit due to radar pulse interference.

[0018]

In order to achieve the above object, the present invention provides a demodulation circuit for demodulating a digitally modulated input signal to a baseband demodulation signal, and a DC offset of the demodulation signal from the outside. Of the DC offset control circuit for controlling according to the offset control signal of No. 1, and the presence or absence of an abnormal state caused by radar pulse interference is detected based on the level change of the output demodulation signal of the DC offset control circuit, and the radar pulse detection signal is detected when the abnormal state is detected. Receiving the output demodulation signal of the DC offset control circuit and the output radar pulse detection signal of the detection circuit means as input signals, and based on the input demodulation signal when the radar pulse detection signal is not input. The offset control signal is generated and the period during which the radar pulse detection signal is input is independent of the input demodulation signal Forcibly generate an offset control signal of the offset value fixed is a more configuration and offset control signal generating means for outputting to the DC offset control circuit.

[0019]

According to the present invention, the detection circuit means detects the presence / absence of an abnormal state caused by radar pulse interference, outputs a radar pulse detection signal when an abnormal state is detected, and the offset control signal generating means has no relation to the demodulated signal. Forcibly generating an offset control signal with a fixed offset value to D
Output to C offset control circuit. Therefore, in the present invention, when an abnormal state due to radar pulse interference is detected, D
The C offset control circuit is substantially prohibited from the offset control operation.

[0020]

Next, an embodiment of the present invention will be described.
FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure,
The same components as those in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted. The embodiment shown in FIG. 1 has a configuration in which the control signal generation circuit 20 is added to the conventional control signal generation circuit 14 with a function of outputting a DC offset detection signal for fixing a DC offset, as compared with the conventional apparatus, and the radar is used. It is characterized in that a radar pulse detection circuit 30 that outputs a radar pulse detection signal when a pulse interference state is detected is added.

That is, the radar pulse detection circuit 30 is
The digital demodulation signal from the / D converter 13 is received as an input signal, and when a radar pulse is detected, a radar pulse detection signal is generated and output to the control signal generation circuit 20. The control signal generation circuit 20 controls the offset as "1" in the positive direction as a DC offset detection signal and DC in the negative direction.
In addition to "-1" for offset control, "0" for fixing the DC offset is output, and "0" is output only when the radar pulse detection signal is input.

As a result, even if the baseband demodulated signal contains an interference signal having a frequency component near DC due to radar pulse interference, the integration circuit 1 during the radar interference duration time
Since the input signal of 5 is only "0", the value of the smoothed DC offset control signal does not respond to the above-mentioned interference signal even during the radar pulse duration and holds the correct value. When the radar pulse detection signal is not input, the control signal generation circuit 20 performs the same operation as the conventional control signal generation circuit 14, detects the DC offset fluctuation of the input digital demodulation signal, and performs offset control in the positive direction. " 1 "or a" -1 "offset detection signal for DC offset control in the negative direction is output.

Next, the structure and operation of the radar pulse detection circuit 30 will be described in more detail. FIG. 2 shows a block diagram of an embodiment of the radar pulse detection circuit 30. The radar pulse detection circuit 30 receives the digital demodulation signal a from the A / D converter 13 and outputs a detection signal b or c indicating whether it is operating in a normal region or an abnormal region. And the continuation time of the normal area detection signal b is measured, and when the first fixed time has elapsed, the normal signal d
And a first counting circuit 32 for outputting the abnormal region detection signal c
And a second counting circuit 33 that outputs a radar pulse detection signal f and an abnormal signal e.

The detection circuit 31 receives the input digital demodulation signal a
Is compared with the specified value of the signal point to determine the state of the received signal. For example, when the A / D converted value of the input digital demodulated signal a has a path 1 signal (MSB), a path 2 signal (2SB) and a path 3 signal (3SB) as shown in FIG. When the input digital demodulated signal a is correctly converged to a specified value (shown by a black circle in FIG. 3), each signal of paths 1 to 3 has an equal value in the following normal region indicated by N in FIG. However, the left end in parentheses is the MSB
Indicates.

(1,1,0), (1,0,1), (0,
1, 0), (0, 0, 1) Therefore, when the combination of the signals of paths 1 to 3 is any of the above, the detection circuit 3
1 outputs a normal area detection signal b. On the other hand, passes 1-3
When the signal combination of is not any of the above, that is, (1,1,1), (1,0,0), (0,1,
The detection circuit 31 outputs the abnormal region detection signal c when any one of the combinations 1) and (0,0,0) within the abnormal region shown in FIG.

The first counting circuit 32 receives the above normal area detection signal b as an input signal, measures the continuous input time thereof, and monitors whether or not the first fixed time has elapsed,
The normal signal d is generated and output when the first constant time has elapsed. The first counting circuit 32 is reset when an abnormal signal e is input from a second counting circuit 33, which will be described later, and stops outputting the normal signal d.

The second counting circuit 33 receives the abnormal area detection signal c and the normal signal d as input signals, and when the abnormal area detection signal c is input for a predetermined time or more after the normal signal d continues. Generates and outputs a radar pulse detection signal f, which is regarded as an abnormal state due to radar pulse interference.

That is, the radar pulse interference is characterized in that it periodically repeats a state in which once it starts to occur, it occurs for a certain time T1 (for example, 1 μsec) and is interrupted for a fixed time T2 (for example, 1 msec). Therefore, the second counting circuit 33 regards the abnormal state within the predetermined time T1 as an abnormal state due to radar pulse interference and generates and outputs the radar pulse detection signal f.

Next, the operation of the second counting circuit 33 in the radar pulse detecting circuit 30 will be described with reference to the flowchart of FIG. First, the second counting circuit 33
If it is determined whether the normal signal d is input from the counting circuit 32 (step 101) and it is determined that the abnormal area detection signal c is input from the detection circuit 31 in the state where the normal signal d is input (( In step 102), it is considered that an abnormal state has occurred due to radar pulse interference, and the radar pulse detection signal f is output (step 103).

Then, the second counting circuit 33 starts measuring the duration of the input abnormal area detection signal c (step 104), and the measurement duration T is the second fixed time (the predetermined time T1). It is monitored whether the above has passed (step 105). When the measurement continuation time T of the abnormal area detection signal c ends or is interrupted within the predetermined time T1, the second counting circuit 33 considers that the radar pulse interference is also interrupted, and outputs the radar pulse detection signal f. Stop (step 106).

On the other hand, when the measurement duration T of the abnormal area detection signal c has exceeded the predetermined time T1, it is considered that an abnormal state has occurred due to a cause other than radar pulse interference, and the second counting circuit 33 An abnormal signal e is generated and output to the first counting circuit 32 (step 107), and this is reset. When the first counting circuit 32 is reset, the output of the normal signal d is stopped, so the second counting circuit 33
Determines in step 101 that the normal signal d has stopped being input,
The output of the radar pulse detection signal f is stopped (step 1
06).

Next, the counting circuit 32, which is a main part of this embodiment.
And the structure and operation of one embodiment of 33 will be described.
FIG. 5 shows a circuit diagram of an embodiment of the counting circuits 32 and 33. In the figure, the same components as those in FIG.
The description is omitted. In FIG. 5, the first counting circuit 3
Reference numeral 2 includes an AND circuit 321 to which the normal area detection signal b and the clock CLK having a constant cycle are input, and a counter 322 that counts the output signal of the AND circuit 321. The counter 322 is reset at the rising edge of the abnormal signal e.

The second counting circuit 33 outputs an abnormal area detection signal c
AND circuit 331 to which the clock CLK is input
A counter 333 that counts the output signal of the AND circuit 331; and an inverter 332 that inverts the polarity of the abnormal area detection signal c and applies it to the reset terminal of the counter 333.
And an AND circuit 334 to which the abnormal area detection signal c and the normal signal d from the counter 322 are input.

With this configuration, when radar pulse interference is occurring, the normal area detection signal b is input as shown in FIG. 6A, and the counter 322 counts the clocks passed through the AND circuit 321. The "H" level normal signal d as shown in FIG. 6B is output, and the AND circuit 334 is placed in the gate "open" state. Therefore, at this time, the input abnormal area detection signal c shown in FIG.
A radar pulse detection signal f is output through the circuit 334 as shown in FIG.

Here, each of the counters 322 and 333 starts counting when the clock CLK is input and outputs an "H" level signal when a certain number is counted, and outputs an "H" level pulse to the reset terminal. When is input, it is reset and counting is started again.

The counter 333 indicates that the abnormal area detection signal c is "
The clock CLK input through the AND circuit 331 is continuously counted during the H "level period (that is,
(The duration of the abnormal area detection signal c is measured.) At the time when the duration of the abnormal area detection signal c counts a fixed number of clocks CLK corresponding to T1, an abnormal state due to a cause other than radar pulse interference is detected. Considering that it has occurred, as shown in FIG. 6D, the "H" level abnormal signal e is output.

As a result, the counter 322 is reset, so that the output normal signal d of the counter 322 (see FIG.
(B)) becomes "L" level, and the AND circuit 334 is in the gate "closed" state. Therefore, passage of the abnormal area detection signal c is blocked by the AND circuit 334, and the output of the radar pulse detection signal f is stopped as shown in FIG. 6 (E).

As described above, according to the present embodiment, only the abnormal state within the predetermined time T1 after the normal state continues in the radar pulse detection circuit 30 is regarded as the abnormal state due to the radar pulse interference and the radar pulse detection is performed. A signal is output, and as a result, “0” is output from the control signal generation circuit 20 and the DC offset control circuit 1 is passed through the integration circuit 15.
Since the offset control operation of No. 2 is substantially prohibited and the offset value is fixed to the previous value, it is possible to prevent a malfunction of the DC offset.

Further, the radar pulse detection circuit 30 stops the output of the radar pulse detection signal in an abnormal state or a normal state other than the above, so that the control signal generation circuit 20 causes the DC offset of the input digital demodulated signal as described above. The integration circuit 1 detects the fluctuation and outputs an offset detection signal.
A DC offset operation is performed by the DC offset control circuit 12 through 5.

Although the above description is for the case of the DC offset control of the two-phase phase modulation system, the present invention is not limited to this, and in the case of the quadrature modulation system, the DC offset control is performed on the in-phase side, It may be expanded to two dimensions on the orthogonal side. In the case of the multi-level quadrature modulation method, the detection circuit 31 may determine the normal area and the abnormal area according to the modulation method.

[0041]

As described above, according to the present invention,
DC is detected when an abnormal condition due to radar pulse interference is detected.
Since the offset control circuit is substantially prohibited from performing the offset control operation, D offset is generated in response to the interference signal included in the demodulated baseband signal due to the radar pulse interference.
It is possible to prevent the C offset control from malfunctioning, so that it is possible to prevent the bit error from occurring easily not only during the duration of the radar pulse interference but also during the interruption time of the radar pulse interference. Further, the normal DC offset operation can be started at the same time when the radar pulse is interrupted.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

2 is a block diagram of an embodiment of a radar pulse detection circuit in FIG.

FIG. 3 is a diagram showing signal points and determination regions for explaining the operation of FIG.

FIG. 4 is a flowchart for explaining an operation of a main part of FIG.

5 is a circuit diagram of an embodiment of the main part of FIG.

FIG. 6 is a time chart for explaining the operation of FIG.

FIG. 7 is a block diagram of a conventional example.

FIG. 8 is a diagram showing signal points and A / D converted values of main parts of FIG. 7.

FIG. 9 is a time chart illustrating a conventional problem.

[Explanation of symbols]

 11 demodulation circuit 12 DC offset control circuit 13 A / D converter 15 integration circuit 20 control signal generation circuit 30 radar pulse detection circuit 31 detection circuit 32 first counting circuit 33 second counting circuit 321, 331 counter

Claims (2)

[Claims] 1. A demodulation circuit that demodulates a digitally modulated input signal to a baseband demodulation signal, and a DC that controls a DC offset of an output demodulation signal of the demodulation circuit according to an offset control signal from the outside. An offset control circuit, detection circuit means for detecting the presence or absence of an abnormal state due to radar pulse interference based on a level change of an output demodulation signal of the DC offset control circuit, and outputting a radar pulse detection signal when the abnormal state is detected; The output demodulation signal of the DC offset control circuit and the output radar pulse detection signal of the detection circuit means are received as input signals, and when the radar pulse detection signal is not input, the offset control signal is based on the input demodulation signal. Is generated, and during the period when the radar pulse detection signal is input, it is forcibly turned on regardless of the input demodulation signal. An offset control signal generating means for generating the offset control signal having a fixed offset value and outputting the offset control signal to the DC offset control circuit. 2. The detection circuit means compares the output demodulated signal of the DC offset control circuit with a prescribed value of a signal point to detect whether the state of the received signal is in a normal region or an abnormal region, A detection circuit that outputs a detection signal corresponding to the detected area, and a duration of the detection signal of the normal area from the detection circuit is measured, and a normal signal is output when the duration has passed a first fixed time. First measuring means for outputting the radar pulse detection signal when the detection signal of the abnormal region is input from the detection circuit when the normal signal is input, and continuing the abnormal region detection signal It is characterized by comprising second measuring means for measuring time and outputting an abnormal signal when the duration has passed a second fixed time and stopping the normal signal output by the first measuring means. Recovery according to claim 1 Adjustment device.