JPS6454798A - Manufacture of ceramic substrate - Google Patents

Manufacture of ceramic substrate

Info

Publication number
JPS6454798A
JPS6454798A JP62210054A JP21005487A JPS6454798A JP S6454798 A JPS6454798 A JP S6454798A JP 62210054 A JP62210054 A JP 62210054A JP 21005487 A JP21005487 A JP 21005487A JP S6454798 A JPS6454798 A JP S6454798A
Authority
JP
Japan
Prior art keywords
substrate
brazing material
silver brazing
tensile strength
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62210054A
Other languages
Japanese (ja)
Inventor
Masahide Okamoto
Hideo Arakawa
Masabumi Ohashi
Satoru Ogiwara
Akira Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62210054A priority Critical patent/JPS6454798A/en
Publication of JPS6454798A publication Critical patent/JPS6454798A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Coupling Device And Connection With Printed Circuit (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Inorganic Insulating Materials (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Multi-Conductor Connections (AREA)

Abstract

PURPOSE:To sinter a substrate, after it is treated, and to improve the tensile strength of a bonded part by filling active metal-added silver brazing material in the through hole of the sintered substrate formed of aluminum nitride, and bonding lead pins through the silver brazing material to the body of the substrate. CONSTITUTION:An integrated circuit element 11 is placed through thin film multilayer interconnections 13 and a solder ball 12 on an AlN substrate 1 with through holes. Active metaladded silver brazing material 2 is filled in the through hole formed of aluminum nitride of the substrate 1. A plurality of lead pins 3 matched to the through holes are bonded through the brazing material 2 by the interconnections 13 or a predetermined jig simultaneously upon filling. The substrate 1 employs a high thermal conductivity AlN sintered plate to reduce a conductive resistance, thereby strengthening the tensile strength of the pin 3 to the substrate 1.
JP62210054A 1987-08-26 1987-08-26 Manufacture of ceramic substrate Pending JPS6454798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62210054A JPS6454798A (en) 1987-08-26 1987-08-26 Manufacture of ceramic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62210054A JPS6454798A (en) 1987-08-26 1987-08-26 Manufacture of ceramic substrate

Publications (1)

Publication Number Publication Date
JPS6454798A true JPS6454798A (en) 1989-03-02

Family

ID=16583048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62210054A Pending JPS6454798A (en) 1987-08-26 1987-08-26 Manufacture of ceramic substrate

Country Status (1)

Country Link
JP (1) JPS6454798A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991016805A1 (en) * 1990-04-16 1991-10-31 Denki Kagaku Kogyo Kabushiki Kaisha Ceramic circuit board
JP2594475B2 (en) * 1990-04-16 1997-03-26 電気化学工業株式会社 Ceramic circuit board
JPH09181423A (en) * 1990-04-16 1997-07-11 Denki Kagaku Kogyo Kk Ceramic circuit board
US5811948A (en) * 1995-08-02 1998-09-22 Nippondenso Co., Ltd. Control apparatus for electric motor
JP2012129238A (en) * 2010-12-13 2012-07-05 Tokuyama Corp Ceramic via substrate, metallized ceramic via substrate, and method for manufacturing both
JP2013115123A (en) * 2011-11-25 2013-06-10 Kyocera Corp Wiring board and manufacturing method therefor
JP2015065442A (en) * 2014-10-27 2015-04-09 株式会社トクヤマ Ceramic via substrate, metallized ceramic via substrate, and method for manufacturing these substrates

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991016805A1 (en) * 1990-04-16 1991-10-31 Denki Kagaku Kogyo Kabushiki Kaisha Ceramic circuit board
US5354415A (en) * 1990-04-16 1994-10-11 Denki Kagaku Kogyo Kabushiki Kaisha Method for forming a ceramic circuit board
JP2594475B2 (en) * 1990-04-16 1997-03-26 電気化学工業株式会社 Ceramic circuit board
JPH09181423A (en) * 1990-04-16 1997-07-11 Denki Kagaku Kogyo Kk Ceramic circuit board
US5811948A (en) * 1995-08-02 1998-09-22 Nippondenso Co., Ltd. Control apparatus for electric motor
JP2012129238A (en) * 2010-12-13 2012-07-05 Tokuyama Corp Ceramic via substrate, metallized ceramic via substrate, and method for manufacturing both
JP2013115123A (en) * 2011-11-25 2013-06-10 Kyocera Corp Wiring board and manufacturing method therefor
JP2015065442A (en) * 2014-10-27 2015-04-09 株式会社トクヤマ Ceramic via substrate, metallized ceramic via substrate, and method for manufacturing these substrates

Similar Documents

Publication Publication Date Title
US7393718B2 (en) Unmolded package for a semiconductor device
US3872583A (en) LSI chip package and method
US6331679B1 (en) Multi-layer circuit board using anisotropic electro-conductive adhesive layer
SG81960A1 (en) Semiconductor device, substrate for a semiconductor device, method of manufacture thereof, and electronic instrument
JPH0258358A (en) Substrate for mounting electronic component
US6555763B1 (en) Multilayered circuit board for semiconductor chip module, and method of manufacturing the same
JPS6473750A (en) Semiconductor device
JPS6454798A (en) Manufacture of ceramic substrate
JPS55111151A (en) Integrated circuit device
JP2000022070A (en) Electronic part having bump and its manufacture
JPS5642362A (en) Package for integrated circuit
JPS6468935A (en) Face-down bonding of semiconductor integrated circuit device
JPS6025910Y2 (en) semiconductor equipment
JPS641268A (en) Ceramic circuit substrate
JPS5598839A (en) Semiconductor device
JP2000022017A (en) Ceramic wiring substrate and package structure thereof
JP3032124U (en) High density bonding pad array integrated circuit package with middle layer
JPS6120356A (en) Semiconductor device
JPH09199621A (en) Temporary semiconductor package including high density array external contact
JPH0239460A (en) Substrate for mounting electronic component
JPS6431444A (en) Porcelain substrate for surface mounting
JPS6414935A (en) Semiconductor device
JPH0740266Y2 (en) Resistor built-in dip switch
JPS5749258A (en) Semiconductor device
JPH01286338A (en) Substrate for mounting electronic parts