JPS6454533A - Processor - Google Patents

Processor

Info

Publication number
JPS6454533A
JPS6454533A JP21169687A JP21169687A JPS6454533A JP S6454533 A JPS6454533 A JP S6454533A JP 21169687 A JP21169687 A JP 21169687A JP 21169687 A JP21169687 A JP 21169687A JP S6454533 A JPS6454533 A JP S6454533A
Authority
JP
Japan
Prior art keywords
ram
instruction
rom
address
corrected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21169687A
Other languages
Japanese (ja)
Inventor
Daisaku Ide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP21169687A priority Critical patent/JPS6454533A/en
Publication of JPS6454533A publication Critical patent/JPS6454533A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To decrease the number of times of the manufacture of a technical sample, and to remarkably shorten the development period, by switching and outputting a substitute program stored in a RAM so as to correspond to a program and an address, in accordance with an instruction at the time of access to a ROM. CONSTITUTION:When a part to be corrected has been generated in a microprogram stored in a ROM 5, in an address of a RAM 6 corresponding to its part, an address of a RAM 7 in which a corrected micro-instruction has been stored in written, and when an address of its part has been designated by an access to the ROM 5, the corrected micro-instruction outputted from the RAM 7 is selected by a selector 9 in accordance with an output signal 103 of the RAM 6 and sent out to an instruction unit 1. In such a way, a partial correction of the program of the ROM 5 can be executed. Also, by storing a branch instruction in the RAM 7, and storing the corrected micro-instruction in a RAM 8, a correction of only a word number portion of the RAM 7 can be executed. By the constitution which considers the capacity balance of said RAM 7 and 8, the performance deterioration is reduced and the correction quantity can be enlarged.
JP21169687A 1987-08-26 1987-08-26 Processor Pending JPS6454533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21169687A JPS6454533A (en) 1987-08-26 1987-08-26 Processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21169687A JPS6454533A (en) 1987-08-26 1987-08-26 Processor

Publications (1)

Publication Number Publication Date
JPS6454533A true JPS6454533A (en) 1989-03-02

Family

ID=16610073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21169687A Pending JPS6454533A (en) 1987-08-26 1987-08-26 Processor

Country Status (1)

Country Link
JP (1) JPS6454533A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423006A (en) * 1990-05-17 1992-01-27 Fanuc Ltd Execution processor for sequence instruction
JPH0581014A (en) * 1990-08-02 1993-04-02 Internatl Business Mach Corp <Ibm> Programmable array for on-chip control store for correcting microcode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423006A (en) * 1990-05-17 1992-01-27 Fanuc Ltd Execution processor for sequence instruction
JPH0581014A (en) * 1990-08-02 1993-04-02 Internatl Business Mach Corp <Ibm> Programmable array for on-chip control store for correcting microcode

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