JPS645449U - - Google Patents
Info
- Publication number
- JPS645449U JPS645449U JP9840387U JP9840387U JPS645449U JP S645449 U JPS645449 U JP S645449U JP 9840387 U JP9840387 U JP 9840387U JP 9840387 U JP9840387 U JP 9840387U JP S645449 U JPS645449 U JP S645449U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wafer
- peripheral edge
- edge portion
- chamfered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Description
第１図は、本考案の一実施例の半導体チツプの
概略構成を示す平面図、第２図は、第１図に示す
―切断線で切断した断面図、第３図は、第２
図の丸印で囲んだ部分の拡大図、第４図及び第５
図は、第１図に示す本実施例の半導体チツプの製
造方法を説明するための図、第６図は、第１図に
示す本実施例の半導体チツプの作用効果を説明す
るための図、第７図及び第８図は、従来の半導体
チツプの問題点を説明するための図である。
図中、１……半導体チツプ、２……表面周辺エ
ツジ部、３……Ｖ字溝、４……切り込み、５……
吸着治具、６……接触部、１０……ウエハ状の半
導体基板である。
1 is a plan view showing a schematic configuration of a semiconductor chip according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the cutting line shown in FIG. 1, and FIG.
Enlarged view of the circled area in the figure, Figures 4 and 5
The figures are diagrams for explaining the manufacturing method of the semiconductor chip of the present embodiment shown in FIG. 1, and FIG. 6 is a diagram for explaining the effects of the semiconductor chip of the present embodiment shown in FIG. FIGS. 7 and 8 are diagrams for explaining problems with conventional semiconductor chips. In the figure, 1...Semiconductor chip, 2...Surface peripheral edge portion, 3...V-shaped groove, 4...Notch, 5...
Suction jig, 6... contact portion, 10... wafer-shaped semiconductor substrate.
Claims (1)
チツプにおいて、その表面周辺エツジ部の少なく
とも１辺以上が面取りされていることを特徴とす
る半導体チツプ。 1. A semiconductor chip cut out from a wafer-shaped semiconductor substrate, wherein at least one side of a peripheral edge portion of the surface of the semiconductor chip is chamfered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9840387U JPS645449U (en) | 1987-06-29 | 1987-06-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9840387U JPS645449U (en) | 1987-06-29 | 1987-06-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS645449U true JPS645449U (en) | 1989-01-12 |
Family
ID=31324634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9840387U Pending JPS645449U (en) | 1987-06-29 | 1987-06-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS645449U (en) |
-
1987
- 1987-06-29 JP JP9840387U patent/JPS645449U/ja active Pending