JPH01167052U - - Google Patents

Info

Publication number
JPH01167052U
JPH01167052U JP1988063301U JP6330188U JPH01167052U JP H01167052 U JPH01167052 U JP H01167052U JP 1988063301 U JP1988063301 U JP 1988063301U JP 6330188 U JP6330188 U JP 6330188U JP H01167052 U JPH01167052 U JP H01167052U
Authority
JP
Japan
Prior art keywords
ceramic substrate
portions
width
end surface
step portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988063301U
Other languages
Japanese (ja)
Other versions
JPH0451485Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988063301U priority Critical patent/JPH0451485Y2/ja
Publication of JPH01167052U publication Critical patent/JPH01167052U/ja
Application granted granted Critical
Publication of JPH0451485Y2 publication Critical patent/JPH0451485Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係るセラミツク基板を用いて
形成した半導体パツケージの斜視図、第２図はそ
の横断面拡大図、第３図は本考案に係るセラミツ
ク基板の要部拡大断面略図、第４図は従来のセラ
ミツク基板の要部拡大断面略図である。 FIG. 1 is a perspective view of a semiconductor package formed using a ceramic substrate according to the present invention, FIG. 2 is an enlarged cross-sectional view thereof, FIG. The figure is a schematic enlarged cross-sectional view of the main part of a conventional ceramic substrate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子を収容するキヤビテイ部を有し、そ
の外周端面のコーナーに微少な丸味が施されてい
る半導体パツケージ用のセラミツク基板であつて
、前記キヤビテイ部が穿設された面と反対側の端
面におけるエツジに、前記セラミツク基板の外周
に沿つて、微少な段差を有する２つの段部と丸味
を施した３つの稜部を形成し、しかも前記２つの
段部を、上方側の第１の段部の幅Ｌ１と、下方側
の第２段部の幅Ｌ２とをＬ１≫Ｌ２の関係に形成
したことを特徴とするセラミツク基板。 A ceramic substrate for a semiconductor package, which has a cavity portion for accommodating a semiconductor element, and has a slightly rounded corner on its outer peripheral end surface, the end surface being opposite to the surface where the cavity portion is bored. Two step portions having a slight step and three rounded ridge portions are formed on the edge along the outer periphery of the ceramic substrate, and the two step portions are connected to the first step portion on the upper side. 1. A ceramic substrate characterized in that the width L 1 of the lower second step portion and the width L 2 of the second step portion on the lower side are formed in a relationship such that L 1 ≫L 2 .
JP1988063301U 1988-05-16 1988-05-16 Expired JPH0451485Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988063301U JPH0451485Y2 (en) 1988-05-16 1988-05-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988063301U JPH0451485Y2 (en) 1988-05-16 1988-05-16

Publications (2)

Publication Number Publication Date
JPH01167052U true JPH01167052U (en) 1989-11-22
JPH0451485Y2 JPH0451485Y2 (en) 1992-12-03

Family

ID=31288809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988063301U Expired JPH0451485Y2 (en) 1988-05-16 1988-05-16

Country Status (1)

Country Link
JP (1) JPH0451485Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0268447U (en) * 1988-11-11 1990-05-24
JP2012119533A (en) * 2010-12-01 2012-06-21 Murata Mfg Co Ltd Ceramic multilayer substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5572064A (en) * 1978-11-25 1980-05-30 Kyocera Corp Ceramic substrate
JPS5750062A (en) * 1980-09-09 1982-03-24 Toshiba Corp Magnetic disk controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5572064A (en) * 1978-11-25 1980-05-30 Kyocera Corp Ceramic substrate
JPS5750062A (en) * 1980-09-09 1982-03-24 Toshiba Corp Magnetic disk controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0268447U (en) * 1988-11-11 1990-05-24
JP2012119533A (en) * 2010-12-01 2012-06-21 Murata Mfg Co Ltd Ceramic multilayer substrate

Also Published As

Publication number Publication date
JPH0451485Y2 (en) 1992-12-03

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