JPS6418733U - - Google Patents

Info

Publication number
JPS6418733U
JPS6418733U JP11303687U JP11303687U JPS6418733U JP S6418733 U JPS6418733 U JP S6418733U JP 11303687 U JP11303687 U JP 11303687U JP 11303687 U JP11303687 U JP 11303687U JP S6418733 U JPS6418733 U JP S6418733U
Authority
JP
Japan
Prior art keywords
chips
chip
semiconductor wafer
semiconductor
corners
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11303687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11303687U priority Critical patent/JPS6418733U/ja
Publication of JPS6418733U publication Critical patent/JPS6418733U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の半導体チツプ用材料の一実
施例をあらわす平面図、第2図は第1図の―
線断面図、第3図はこの実施例の半導体チツプ用
材料から切り出された半導体チツプをあらわす斜
視図、第4図は従来の半導体チツプ用材料の一例
をあらわす平面図、第5図はこの従来例の半導体
チツプ用材料から切り出された半導体チツプをあ
らわす平面図である。 1……パツシベーシヨン膜、1a……パツシベ
ーシヨン膜角部、A……半導体チツプ用材料、E
……素子。
Fig. 1 is a plan view showing an embodiment of the semiconductor chip material of this invention, and Fig. 2 is a plan view of the semiconductor chip material of this invention.
3 is a perspective view showing a semiconductor chip cut out from the semiconductor chip material of this embodiment, FIG. 4 is a plan view showing an example of a conventional semiconductor chip material, and FIG. 5 is a plan view showing an example of the conventional semiconductor chip material. FIG. 2 is a plan view showing a semiconductor chip cut out from an example semiconductor chip material. 1... Passivation film, 1a... Passivation film corner, A... Material for semiconductor chip, E
……element.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体ウエハを多数のチツプに分割した際それ
ぞれのチツプ上に実装されるべき多数の素子が前
記半導体ウエハ上に形成され、この各素子を覆う
よう各チツプに相当する半導体ウエハ表面がチツ
プの数だけのパツシベーシヨン膜で被覆されてな
る半導体チツプ用材料であつて、分割後のチツプ
角部に相当するパツシベーシヨン膜角部が滑らか
な曲面を描いて一辺から他辺に繋がれていること
を特徴とする半導体チツプ用材料。
When a semiconductor wafer is divided into a large number of chips, a large number of elements to be mounted on each chip are formed on the semiconductor wafer, and the surface of the semiconductor wafer corresponding to each chip is covered with the same number of chips as the number of chips. A semiconductor chip material coated with a passivation film, characterized in that the corners of the passivation film corresponding to the corners of the chip after division form a smooth curved surface and are connected from one side to the other. Materials for semiconductor chips.
JP11303687U 1987-07-22 1987-07-22 Pending JPS6418733U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11303687U JPS6418733U (en) 1987-07-22 1987-07-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11303687U JPS6418733U (en) 1987-07-22 1987-07-22

Publications (1)

Publication Number Publication Date
JPS6418733U true JPS6418733U (en) 1989-01-30

Family

ID=31352519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11303687U Pending JPS6418733U (en) 1987-07-22 1987-07-22

Country Status (1)

Country Link
JP (1) JPS6418733U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997047029A1 (en) * 1996-06-07 1997-12-11 Rohm Co., Ltd. Semiconductor chip and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997047029A1 (en) * 1996-06-07 1997-12-11 Rohm Co., Ltd. Semiconductor chip and method for manufacturing the same

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