JPH02142536U - - Google Patents
Info
- Publication number
- JPH02142536U JPH02142536U JP1989051154U JP5115489U JPH02142536U JP H02142536 U JPH02142536 U JP H02142536U JP 1989051154 U JP1989051154 U JP 1989051154U JP 5115489 U JP5115489 U JP 5115489U JP H02142536 U JPH02142536 U JP H02142536U
- Authority
- JP
- Japan
- Prior art keywords
- package
- lid
- metallized layer
- package body
- wide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 5
- 238000005219 brazing Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Casings For Electric Apparatus (AREA)
Description
第１図は本考案の一実施例による半導体素子収
納用パツケージの断面概略構成図、第２図及び第
３図は従来の半導体素子収納用パツケージの第１
図に相当する図である。
１……パツケージ本体、２……半導体素子、５
……パツケージ本体側封止用メタライズ層、６…
…蓋板、７，８……蓋体側封止用メタライズ層、
９……ろう材。
FIG. 1 is a schematic cross-sectional view of a semiconductor device storage package according to an embodiment of the present invention, and FIGS. 2 and 3 are a first diagram of a conventional semiconductor device storage package.
FIG. 1...Package body, 2...Semiconductor element, 5
...Package main body side sealing metallized layer, 6...
...Lid plate, 7, 8...Metallized layer for lid side sealing,
9...Brazing material.
Claims (1)
体を有し、このパツケージ本体及び蓋体のそれぞ
れの対向する部分に、両者をろう付けするための
封止用メタライズ層が形成された半導体素子収納
用パツケージであつて、 前記蓋体に形成されたメタライズ層の前記パツ
ケージ本体に対向する部分の封止幅は、前記パツ
ケージ本体に形成されたメタライズ層の封止幅よ
りも広くなつている、 ことを特徴とする半導体素子収納用パツケージ。[Claims for Utility Model Registration] A package that has a package body and a lid on which a semiconductor element is mounted, and a sealing metallized layer for brazing the two on opposing parts of the package body and the lid, respectively. In the formed package for storing semiconductor elements, the sealing width of a portion of the metallized layer formed on the lid body facing the package body is wider than the sealing width of the metallized layer formed on the package body. A package cage for storing semiconductor elements, which is characterized by being wide and wide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989051154U JPH02142536U (en) | 1989-04-28 | 1989-04-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989051154U JPH02142536U (en) | 1989-04-28 | 1989-04-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02142536U true JPH02142536U (en) | 1990-12-04 |
Family
ID=31570336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989051154U Pending JPH02142536U (en) | 1989-04-28 | 1989-04-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02142536U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015192097A (en) * | 2014-03-28 | 2015-11-02 | 住友電工デバイス・イノベーション株式会社 | Package for mounting electronic component |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60115247A (en) * | 1983-11-28 | 1985-06-21 | Fujitsu Ltd | Semiconductor device |
-
1989
- 1989-04-28 JP JP1989051154U patent/JPH02142536U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60115247A (en) * | 1983-11-28 | 1985-06-21 | Fujitsu Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015192097A (en) * | 2014-03-28 | 2015-11-02 | 住友電工デバイス・イノベーション株式会社 | Package for mounting electronic component |