JPS645241A - Terminator - Google Patents

Terminator

Info

Publication number
JPS645241A
JPS645241A JP16214187A JP16214187A JPS645241A JP S645241 A JPS645241 A JP S645241A JP 16214187 A JP16214187 A JP 16214187A JP 16214187 A JP16214187 A JP 16214187A JP S645241 A JPS645241 A JP S645241A
Authority
JP
Japan
Prior art keywords
signal
data
transmission
timing
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16214187A
Other languages
Japanese (ja)
Other versions
JPH0585093B2 (en
Inventor
Toshimichi Shimatani
Yoshihiro Kawada
Tomoyuki Ujiie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Iwatsu Electric Co Ltd
Original Assignee
Iwatsu Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iwatsu Electric Co Ltd filed Critical Iwatsu Electric Co Ltd
Priority to JP16214187A priority Critical patent/JPS645241A/en
Publication of JPS645241A publication Critical patent/JPS645241A/en
Publication of JPH0585093B2 publication Critical patent/JPH0585093B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To attain communication via a PCM transmission line for various terminal equipments with different data speed by synchronizing the operation of a terminal equipment with the PCM transmission line, mapping a data signal of the terminal equipment to apply speed conversion and sending the result to the PCM transmission line. CONSTITUTION:A PLL (phase locked loop) circuit 100 generates a basic lock 121 to obtain various timing signals in an equipment based on the XSYN (transmission synchronizing signal) of the PCM transmission line. A mapping circuit 300 maps a transmission data SD, a transmission request signal RS, a transmission enable signal CS', a data terminal ready signal ER and a called display signal CI' by using a bus signal 259 and a signal 274. A de-mapping circuit 400 demaps the reception data RD in the timing of signals 262 and 275, the transmission enable signal CS, data set ready signal DR and the called display signal CI in the timing of the bus signal 286 and the reception carrier detection signal CD in the timing of the signal 264 to send the result to a terminal equipment.
JP16214187A 1987-06-29 1987-06-29 Terminator Granted JPS645241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16214187A JPS645241A (en) 1987-06-29 1987-06-29 Terminator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16214187A JPS645241A (en) 1987-06-29 1987-06-29 Terminator

Publications (2)

Publication Number Publication Date
JPS645241A true JPS645241A (en) 1989-01-10
JPH0585093B2 JPH0585093B2 (en) 1993-12-06

Family

ID=15748814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16214187A Granted JPS645241A (en) 1987-06-29 1987-06-29 Terminator

Country Status (1)

Country Link
JP (1) JPS645241A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57183147A (en) * 1981-04-30 1982-11-11 Ibm Data transmitter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57183147A (en) * 1981-04-30 1982-11-11 Ibm Data transmitter

Also Published As

Publication number Publication date
JPH0585093B2 (en) 1993-12-06

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Legal Events

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