JPS6451636A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To miniaturize an element isolation region, and to improve the degree of integration of an integrated circuit by depositing polysilicon onto the sidewall of an opening section in an oxide film, etching a nitride film in narrow width, using the oxide film, the size of the opening section of which is narrowed through oxidation, as a mask and employing the nitride film as a mask for selective oxidation. CONSTITUTION:An oxide film 2 for relaxing stress is formed onto an silicon substrate 1, and a nitride film 3 is deposited onto the oxide film 2. An oxide film 4 is deposited, and lastly the oxide film 4 is coated with an etching mask 5. An oxide film 4a is etched to shape an opening section 4b. Polysilicon 6 is deposited, and polysilicon 6a is etched so as to be left only on the sidewall of the oxide film 4a through anisotropic etching. The width of an opening section 6b is brought to approximately 0.6 micron at that time. Polysilicon is oxidized to shape an oxide film 7. The width of an opening section 7a is brought to approximately 0.2 micron after oxidation. A nitride film 3a is etched, using the oxide film 4a as a mask. Lastly, an oxide film 2a is formed through selective oxidation, employing the nitride film 3a as a mask, thus shaping an element isolation region.