JPS6448517A - Biphase clock generating circuit - Google Patents

Biphase clock generating circuit

Info

Publication number
JPS6448517A
JPS6448517A JP62204522A JP20452287A JPS6448517A JP S6448517 A JPS6448517 A JP S6448517A JP 62204522 A JP62204522 A JP 62204522A JP 20452287 A JP20452287 A JP 20452287A JP S6448517 A JPS6448517 A JP S6448517A
Authority
JP
Japan
Prior art keywords
channel mos
generating circuit
clock generating
inverter
biphase clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62204522A
Other languages
Japanese (ja)
Inventor
Yasushi Wakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62204522A priority Critical patent/JPS6448517A/en
Publication of JPS6448517A publication Critical patent/JPS6448517A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To reduce the chip area by constituting the titled circuit by two P- channel MOS transistors(TRs), two N-channel MOS TRs and 5 inverters. CONSTITUTION:The source of a 1st P-channel MOS TR 2 is connected to an input terminal 1 and the gate is connected to the output of a 1st inverter 11 respectively. The gate of a 1st N-channel MOS TR 3 is connected to the output of a 2nd inverter 7 and the source is connected to a negative power supply 13 respectively and the input 4 of a 3rd inverter 4 is connected to the drain of the 1st N-channel MOS TR 3 and the drain of the 1st P-channel TR 2. Moreover, the 2nd P-channel MOS TR 8 and the N-channel MOS TR 9 are provided. Thus, the chip area is reduced.
JP62204522A 1987-08-18 1987-08-18 Biphase clock generating circuit Pending JPS6448517A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62204522A JPS6448517A (en) 1987-08-18 1987-08-18 Biphase clock generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62204522A JPS6448517A (en) 1987-08-18 1987-08-18 Biphase clock generating circuit

Publications (1)

Publication Number Publication Date
JPS6448517A true JPS6448517A (en) 1989-02-23

Family

ID=16491927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62204522A Pending JPS6448517A (en) 1987-08-18 1987-08-18 Biphase clock generating circuit

Country Status (1)

Country Link
JP (1) JPS6448517A (en)

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