JPS644217B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a distributed computer system,
In particular, the present invention relates to a distributed computer system in which a plurality of lower-level computers are connected to a higher-level computer.

Conventional forms of distributed computer systems include a loop shape as shown in FIG. 1, a cascade shape as shown in FIG. 2, and a combination of a loop shape and a cascade shape as shown in FIG. In the loop system shown in FIG. 1, a data way 2 is arranged in a loop around a processing device 1, stations 3 are provided here and there, and terminal input/output devices 4 are connected to the stations 3.

In addition, the cascade system shown in FIG. 2 connects the first terminal input/output device (or lower-level computer) to the first terminal input/output device (or lower-order computer) through the data way 6 to the processing device ₅ , and then connects another terminal input device ₇₂ to the ₁ , successive terminal input/output devices are connected to the preceding terminal input/output device, and finally 7 ₁ to 7n are connected in cascade.

Furthermore, FIG. 3 shows a combination system, in which a data way 9 is first arranged in a loop for the upper processing device 8, and then a plurality of stations 1 are arranged at predetermined locations.
A lower processing device 11 is connected to this station 10, and terminal input/output devices (or processing devices) 13 ₁ to 13n are sequentially connected to this lower processing device 11 via a data way 12 as shown in FIG. It is something that connects.

Each of the systems described above has drawbacks as specifically described below.

In other words, in the system shown in Figure 1, multiple processing devices are connected to the same transmission path, so when one processing device receives interference from another, it is difficult to determine which processing device is the culprit. Independence is not maintained.

In addition, in the system shown in Figure 2, especially high-speed
In applications such as DDC (rolling mill control), slow transmission speed is critical. The main reason for this is that when many CPUs use one line, overhead time is required for calling stations and procedures for exclusive use of the line, making it impossible to increase the transmission speed. Transmission overhead typically occupies more than 90% of the total transmission time.

For this reason, in controlling rolling mills, etc., sequence logic processing including relatively simple numerical calculations is handled by the lower-level microcomputer, while relatively difficult and advanced calculation processing is performed by the higher-level control computer. It consists of In this case, although the host computer itself has high speed and advanced functions, the speed of the transmission device is not sufficient, so DDC-like control by the host computer is often virtually impossible.

Furthermore, the system shown in FIG. 3 has the drawbacks of the systems shown in FIGS. 1 and 2 above.

Recent control system configurations have become more sophisticated, with distributed processing performed by microcomputers and simultaneous calculation of overall process information using sophisticated control devices to optimally control the entire plant. In other words, high-speed processing equipment including transmission equipment performs distributed processing,
It has become essential to have a control device that has both advantages of centralized processing.

Also, according to recent system configurations, it is a reality that process signals are required to be synchronized and shared by both the lower-level microcontroller and the higher-level control computer, and how can the process signals be shared? There is also an issue regarding how to do this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a distributed computer system that can minimize system dead time between upper and lower processing units.

The present invention provides registers that can arbitrarily write and read data from a process input/output device between a lower-level computer, a terminal, and a higher-level computer, and distribute signals to these registers by a logic controller. Process signals are shared between the processing device and the higher-level processing device.

FIG. 4 is a block diagram showing an embodiment of the present invention.

The higher-level processing device includes a global memory 21, a higher-level computer 22 connected to the memory 21, a higher-level combiner 23 connected to the global memory 21 (a multiplexer 231 for switching a group of lower-level processing devices,
(consisting of a memory combiner 232).
A transmission device for connecting a plurality of lower processing devices is connected to the multiplexer 231.

The transmission device is composed of a coupler 24 ₁ (consisting of a multiplexer 241 ₁ and a plant controller coupler 242 ₁ ) connected to a higher-level processing device, and a plant controller 25 ₁ . multiplexer 2
41 ₁ is the terminal input/output device 26 ₁ , 26 ₂ to be connected
The plant controller coupler 242 ₁ functions as an I/O device for the plant controller 25 ₁ . A microcomputer is used as the plant controller ₂₅₁ . A plurality of transmission devices are provided corresponding to each control section of a processing target (for example, a rolling plant). For example, the control divisions are a heating furnace zone, a rough rolling mill zone, and a finishing mill zone. Signals from transmission devices #1 to #n are sent to upper combiner 2 by multiplex transmission.
3. The aggregated signal is transferred to a global memory 21, which is a common symbol device, at a constant sampling pitch. A large control computer is connected to this global memory 21 as a host computer, and performs high-level arithmetic processing that cannot be processed at the microcomputer level of the plant controller. Processing by the lower-level microcomputer is mainly conventional electrical control (sequence control), simple numerical calculations, etc.

As shown in this example, the dendritic transmission network facilitates hierarchical processing, i.e. microcomputer electrical control large control computer - advanced arithmetic processing (
(control theory processing, etc.) is cyclically applied to each gate, whereby all lower level signal groups are converted into serial signals and transmitted to the upper level.

FIG. 5 is a detailed block diagram of the transmission device.

A pair of multiplexers 31 on the bus line 30,
32 are connected via gates 311 and 312. Further, a plant controller 33 is connected to the bus line 30. Multiplexer 31, 32
A logic controller 34 is connected to each of them via gates 341 and 342, and switches registers provided corresponding to the connected devices and devices. A plurality of registers 35 are connected to the multiplexer 31, and the parallel outputs of these registers are connected to the parallel/serial converter 3.
6 to the upper combiner 23. On the other hand, multiple registers 37 are also provided for the multiplexer 32.
is connected, and the parallel output of this register is connected to a parallel-to-serial converter 38. The serial conversion side of the parallel/serial converter 38 is connected to the terminal input/output device 26 shown in FIG.
Any one of ₁ to 26n is connected.

Logic controller 34 instructs multiplexers 31 and 32 sequentially or selectively to transfer data to predetermined addresses in registers 35 and 37. The plant controller 33 acquires necessary data from each register via the bus line 30. The registers 35 and 37 are readable and writable, and function as if they had two independent blocks of memory, and are generally referred to as dual port registers. 311,
312 and gates 341 and 342. With such a configuration,
While independence and isolation of input/output signals are ensured between the input/output of the lower-level plant controller and the higher-level control computer, the system allows process input/output signals to be shared between the higher-level computer and the lower-level microcontroller. ing.

The transmission device shown in FIG. 5 and the terminal input/output device are connected by multiplex transmission as shown in FIG. 6. The example shown here is an example of 1:1 type multiplex transmission, and the plant signal is sent to the plant terminal (e.g. electric motor, hydraulic valve, etc.).
Multiple signals, such as signals from detectors (limit switches, thermal mass detectors, operating switches, etc.), change independently of each other over time, and are usually parallel signals. Therefore, the signal conditioner 40
A group of detection signals taken in from the plant terminal are converted into a temporally serial pulse train by a parallel/serial converter 41, and transmitted to a serial/parallel converter 38 on the transmission device side. Parallel-to-serial conversion by the parallel-to-serial converter 41 is performed at every fixed sampling pitch. In the transmission device, data is rewritten at regular intervals according to data on the terminal side.
This writing will be explained with reference to FIG.

The output signal from the parallel/serial converter 41 on the terminal input/output device side is transmitted to the serial/parallel converter 38 in the transmission device. The parallel output signal converted by the serial/parallel converter 38 is written into the register 37.
Any output from any of the plurality of serial/parallel converters 38 is stored in the corresponding register 37. At this time, the multiplexer 32 is switched according to instructions from the logic controller 34, and stores the output of the serial/parallel converter 38 at a predetermined address. The transmission unit in this case is 32 to 256 points. Corresponding to this,
The upper linkage has a transmission unit of 1024 to 2048 points. Also, for lower linkage, 1 to
It is rewritten at a sampling pitch of about 2mS, but the upper linkage has a large amount of data, but
It is necessary to secure a sampling pitch of about 2 mS. Technically, this only increases the speed of the transmission line (for example, optical transmission), and the configuration of the present invention itself cannot become a dead time for the transmission.

Above, I have described up to writing to the register, but
Next, the operation of the logic controller and multiplexer will be explained based on FIG.

When data has been written to each register 37, the logic controller 34 outputs a gate signal.
G ₁ -Gn are applied sequentially to multiplexers 32 and 31, and both multiplexers are switched synchronously. As a result, the contents of one of the registers 37 is transferred to the register 35 via the multiplexer 31. Further, since the logic controller 34 is capable of selecting a single register, each address of the register 37 can be specified arbitrarily to perform writing or reading. Therefore, it is possible to read the previous information at the same time as writing information from the terminal, and it is also possible to link the same data contents as if mirroring them. The register 35 also has this function. Further, the registers 35 and 37 can be accessed arbitrarily. Therefore, it can be accessed without any overhead time.

In this way, it is possible to share process signals between the lower-level plant controller and the higher-level control computer. In addition, the links of the transmission system are high-speed transmissions, and optical transmission is used especially for aggregated transmissions to prevent a drop in transmission speed at upper branches. By doing so, the entire status of the lower process input/output devices can be grasped, especially in the upper coupler. The host computer can perform optimal control over the entire plant using all process data. It is possible to bring out the features of a so-called centralized control device. In the configuration of a control system, centralization as well as decentralization are important, and the ability to easily achieve this is a major feature of a dendritic transmission network. The dendritic transmission network control device enables system configurations that are optimal for systems that require high-speed DDC processing, called centralized, distributed, and hierarchical systems.

As is clear from the above, the embodiments of the present invention have the advantages of a centralized system, a distributed system, and a hierarchical system, and also enable high-speed DDC control that requires high-level arithmetic processing. The system can be realized.

Conventionally, such a system required a large number of cables to be installed radially (one core per minimum 1 bit), but according to the present invention, both the amount of cables and construction costs can be significantly reduced compared to the conventional system. can.

According to the present invention, system dead time can be minimized by providing a transmission device that can share a process input/output device between a lower-level processing device and a higher-level processing device.

[Brief explanation of drawings]

Figure 1 is a system diagram of a conventional loop-shaped distributed computer system, Figure 2 is a system diagram of a conventional cascade-shaped distributed computer system, Figure 3 is a system diagram of a conventional third distributed computer system, and Figure 2 is a system diagram of a conventional cascade-shaped distributed computer system. Figure 4 is a block diagram showing an embodiment of the present invention;
FIG. 5 is a detailed block diagram of a transmission device according to the present invention, FIG. 6 is a circuit diagram showing an example of a transmission format with a terminal, and FIG. 7 is a diagram for explaining a write operation according to an embodiment of the present invention. Terminal Side Block Diagram FIG. 8 is a peripheral block diagram of a multiplexer for explaining data transfer in an embodiment of the present invention. 21... Global memory, 22... Upper computer, 23... Upper combiner, 24... Combiner, 25
₁ ~25n, 33...Plant controller, 2
6 ₁ to 26n... terminal input/output device, 30... bus line, 31, 32, 241... multiplexer, 34... logic controller, 35, 37
...Register, 36, 38...Parallel/serial converter.

Claims (1)

[Claims] 1. In a distributed computer system comprising a host computer that performs integrated control, and multiple lower-order computers that are connected to the host computer and perform lower-level control at high speed based on data from terminals. , a first register group connected to the terminal device and capable of writing and reading information therefrom; and a first register group connected to the host computer via an upper combiner and a common storage device and capable of writing and reading information therefrom; a second register group that is capable of
a multiplexer that is connected to a group of registers and switches the contents of the registers; a logic controller that outputs an instruction for switching the contents of the registers to the pair of multiplexers sequentially or selectively according to a built-in control program; A distributed computer system comprising: a pair of multiplexers and a bus connecting the lower-level computer.