JPS6442167A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS6442167A
JPS6442167A JP62198566A JP19856687A JPS6442167A JP S6442167 A JPS6442167 A JP S6442167A JP 62198566 A JP62198566 A JP 62198566A JP 19856687 A JP19856687 A JP 19856687A JP S6442167 A JPS6442167 A JP S6442167A
Authority
JP
Japan
Prior art keywords
bit line
word line
line
bit
groove part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62198566A
Other languages
Japanese (ja)
Inventor
Yoshiki Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62198566A priority Critical patent/JPS6442167A/en
Priority to US07/232,641 priority patent/US4912535A/en
Publication of JPS6442167A publication Critical patent/JPS6442167A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To facilitate the pattern transfer and processing for a bit line and a word line without requiring any complicated manufacture process by electrically connecting the bit wire to the other electrode of a transfer gate transistor through a groove part and forming the word line on a storage node and on the bit line via an insulating film. CONSTITUTION:A bit line 12b is electrically connected with the other electrode 15 of a transfer gate transistor through a groove part 2. Hereby, there is required no separate electrical connector means such as a contact part, and there are produced no steps on the groove part due to the bit line. Additionally, a word line 10 is formed via an insulating film 17 formed on a storage node 12a and the bit line 12b. Hereby, the device can be manufactured without consideration of electrical contact of the word line with the surface node 12a and the bit line 12b upon formation of the word line 18. Thus, pattern transfer and processing of the bit line and word line is facilitated, assuring high density and larger integration of the device.
JP62198566A 1987-08-08 1987-08-08 Semiconductor memory device Pending JPS6442167A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62198566A JPS6442167A (en) 1987-08-08 1987-08-08 Semiconductor memory device
US07/232,641 US4912535A (en) 1987-08-08 1988-08-08 Trench type semiconductor memory device having side wall contact

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62198566A JPS6442167A (en) 1987-08-08 1987-08-08 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS6442167A true JPS6442167A (en) 1989-02-14

Family

ID=16393310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62198566A Pending JPS6442167A (en) 1987-08-08 1987-08-08 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS6442167A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410169A (en) * 1990-02-26 1995-04-25 Kabushiki Kaisha Toshiba Dynamic random access memory having bit lines buried in semiconductor substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS561560A (en) * 1979-06-19 1981-01-09 Sanyo Electric Co Ltd Semiconductor memory cell

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS561560A (en) * 1979-06-19 1981-01-09 Sanyo Electric Co Ltd Semiconductor memory cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410169A (en) * 1990-02-26 1995-04-25 Kabushiki Kaisha Toshiba Dynamic random access memory having bit lines buried in semiconductor substrate

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