JPS6439890A - Image compressing and encoding circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit and to reduce a circuit scale by transmitting a clock to serial-shift variable length code data to be parallely outputted and executing conversion to the data arrangement of the packing of encode data and a fixed length bit. CONSTITUTION:Image data, which is synchronized with an image data input clock and inputted, are loaded through adding and subtracting circuits 8 and 9 and an encoding ROM10 to a parallel/serial converting register 11 as encoding data and in the same timing, the data of an encoding bit number are loaded to a down-counter 12. A serial shift reference clock executes a down-count simultaneously with the setting of the data to the down-counter 12. This serial clock, which outputs a serial shift clock only for the encoding bit numbers through a gate 15 to the parallel/serial converting register 11 and a serial/ parallel converting register 13 until this value goes to zero, is counted in a up-counter 14 and goes to be the bite count signal of an allowing signal to write the data of the register 13 to an image buffer 6 for the unit of eight clocks. By this signal, the variable length encoding data packed in the unit of eight bits are recorded to the image buffer 6.