JPH02302193A - Picture encoder - Google Patents

Abstract

PURPOSE:To reduce the scale of a circuit actually operated at a high speed to make the whole of a device small in size and low in cost by temporarily converting a variable length code to a parallel signal having a fixed bit width without converting it to a serial signal and converting the parallel signal to a serial signal just before transmission to a transmission line. CONSTITUTION:A variable/fixed parallel converter 13 converts the multiplexed variable length code to the parallel signal having the fixed bit width. An output signal 112 having the k-bit fixed width ((k) is a natural number) is written in a transmission buffer 14 with the output strobe as the control signal. The signal is read out from the transmission buffer 14 at a speed fT/k(b/s) when the transmission speed of the transmission line is set to fT(b/a), and the signal is converted to the serial signal by a parallel/serial converter 15 and is outputted to the transmission line. As the result, the processing is performed at a sufficiently allowable low speed though the transmission speed fT of the transmission line is considerably high, and it is unnecessary to extend the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an image encoding device, and particularly to an image encoding device applied to video conferences, video telephones, and the like.

[Conventional technology]

Figure 4 shows, for example, literature, the Institute of Electronics, Information and Communication Engineers Spring National Conference (
1989) Proceedings D-104r Moving Image Coding Using Adaptive Quantization Characteristic Control” is an encoding block diagram shown in
In the figure, (1) is an input buffer that inputs a digitized image signal, converts it to a scanning order suitable for encoding, and outputs it, and (2) represents the input image signal after encoding and decoding one frame before. a frame memory that stores image signals of (3)
) is a motion compensation prediction unit that performs motion compensation prediction and outputs a motion vector (109) and a pre-a-1 signal (103);
4) is the pre-flPl signal (103) and the input image signal (10
1) an interframe subtractor that performs the difference calculation and outputs an interframe difference signal (104); (5) a quantization/encoding unit that quantizes and encodes the interframe difference signal (104);
(6) is a quantization/decoding unit that decodes the quantized/encoded signal (105), and (7) is an interframe adder that adds the predicted signal (103) and the quantized/decoded signal (106). ,
(8a) and (8b) are the quantized and encoded signals (105
), the first .
The second variable length encoding unit (9) has two types of variable length codes (1
0″B), a multiplexing unit that multiplexes (110), (l
O) is a speed conversion buffer that manually inputs the multiplexed signal (111), and (11) is a speed conversion buffer (10).
A parallel/serial converter (12) is a transmission buffer that converts a parallel signal outputted from a serial signal into a serial signal.

Next, the operation will be explained. The input digital image signal is stored in the input buffer (1) and then read out in blocks (a x b) in pixel units suitable for the subsequent motion compensator ΔPj (a).

b = natural number). The read input image signal (101) is input to the motion compensation prediction unit (3).

The motion compensation prediction unit (3) reads the previous image signal (102) corresponding to a plurality of blocks including the same position on the screen as the human image signal (101) from the frame memory (2), and reads the input image signal (101) from the frame memory (2). ) and a plurality of previous image signals (102
) is calculated. For example, (a
X b) The sum of absolute differences between pixel data at the same position in a block of pixels is used.

As a result of distortion calculation, the previous screen data with the smallest distortion (102)
is selected and output as a prediction signal (103), and at the same time the position of the selected previous screen data (102) on the screen is converted into a displacement from the position of the input image signal (101), the motion vector ( 109).

The input image signal (101) and the pre-al signal (103) are input to an interframe subtracter (4), where they are subtracted and become an interframe difference signal (IO2). This interframe difference signal (
104) is manually input to a quantizer/encoder (5) and becomes a quantized/encoded signal (105).

As a quantization/encoding method, a discrete cosine transform (DCT) or the like as shown in the above-mentioned document is used.

The quantized/encoded signal (105) is sent to the variable length encoder (8a
) is converted into a variable length code (108) according to the probability of occurrence.

On the other hand, the motion vector (109) is also
) is converted into a variable length code (110).

The variable length code (108) and the variable length code (110) are multiplexed in the transmission order in the multiplexer (9) and output as a multiplexed signal (111).

The multiplexed signal (111) is sent to the speed conversion buffer (1o).
After being stored, it is read out as appropriate, converted into a serial signal (113) by a parallel/serial converter (11), stored in a transmission buffer (12), and read out in accordance with the speed of the transmission line.

The quantized/encoded signal (105) is sent to the variable length encoder (8a
), it is also input to the quantization/decoding section (6), where it is decoded and becomes a quantized/decoded signal (106). This quantized decoded signal (106) and the predicted signal (1
03) is input to the interframe adder (7) and added, resulting in an encoded/decoded image signal (lO7) and stored in the frame memory (2).

In the apparatus for encoding the interframe difference signal (104) as described above, a large amount of information is generated in a large part of the interframe difference signal (104), in other words, in a part of the screen where there is large movement. This situation will be explained using FIG.

FIG. 5 <a> is an example in which a region of 8 pixels by 8 pixels on the screen is treated as one block, and motion compensation and discrete cosine transformation are applied to each block.

In this example, as shown in FIG. 5(b), the block (
In blocks 1), (2), (4), and (5), the interframe difference signal is small and the amount of code generated is very small as a result of variable-length encoding, whereas in block (3), a large amount of code is generated. ing. Multiplexed signal for each block (111)
Assuming that the output cycle of is 10 seconds and the maximum variable length code amount per block is nobit, in order to perform parallel/serial conversion without stagnation, it is necessary to perform processing at a cycle of to/no seconds.

This tO/nO period processing is much faster than the processing period of the entire encoding device, leading to an increase in circuit scale.
It also has problems such as the need for high-speed elements.

For this reason, the speed conversion buffer (1G ).

In devices currently in practical use, the pixel clock of the input image (number of input pixels: 7 seconds) is generally oafT, where the speed of the fO1 encoded signal on the transmission path is fT (b/s). It is. In other words, the input image is 1 bit
It is compressed to less than / pixel. Therefore, if you use the speed conversion buffer (10), the pixel clock (or its frequency divided version) will be used up to the writing side of the transmission buffer (12).
It is now possible to use

[Problem to be solved by the invention]

Conventional image encoding devices are configured as described above, so when it is desired to transmit a high-quality image over a wideband transmission path, that is, when the degree of compression of the input image is low, the amount of generated code can be reduced. Since there are fewer blocks with fewer codes and the maximum number of blocks with a larger amount of generated codes increases, the time conversion effect of the speed conversion buffer cannot be expected, and the parallel/serial converter (11) and transmission buffer (12) are not operated at high speed. There is a problem in that the circuit must be operated, which increases the circuit scale.

This invention has been made to solve the above-mentioned problems, and even in high-quality image encoding devices with high transmission speeds, parallel/serial conversion of variable length codes and input into transmission buffers are required. The purpose of the present invention is to keep the output speed relatively low, configure the corresponding part with a small-scale circuit without using high-speed elements, and obtain an image encoding device that is small and inexpensive as a whole.

[Means to solve the problem]

An image encoding device according to the present invention includes a variable/fixed parallel converter that converts a variable length encoded signal into a fixed bit width parallel signal without converting it into serial data, and stores the parallel signal in a transmission buffer; It is equipped with a parallel/serial converter that converts a fixed bit width barrel signal read from a transmission buffer into a serial signal and sends it to a transmission path.

[Effect]

The image encoding device in this invention converts a variable length code into a fixed bit width parallel signal, stores it in a transmission buffer, reads it from the transmission buffer, performs fixed bit width parallel/serial conversion, and sends it to a transmission path. By sending serial signals, even if the transmission speed of the transmission line is high, processes other than parallel/serial conversion can be performed at low speeds, making it possible to reduce the circuit scale.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In Figure 1, (1) is a manual buffer that inputs a digitized image signal, changes the scanning order suitable for encoding, and outputs it, and (2) encodes/decodes the previous frame of the input image signal. Frame memory for storing subsequent image signals (3
) is a motion compensator C1 unit that performs motion compensation prediction and outputs a motion vector (109) and a prediction signal (103);
) is the pre-Δ-1 signal (103) and the input image signal (101)
(5) is a quantization/encoding unit that quantizes and encodes the interframe difference signal, and (6) is a quantization/encoding unit that performs a difference calculation and outputs an interframe difference signal (104). A quantization/decoding unit that decodes the encoded signal (105), (7) an interframe adder that adds the pre-JIIJ signal (103) and the quantized/decoded signal (106), (8a)
, (8b) are each quantized/encoded signal <105)
, first and second variable-length encoding units that variable-length encode the motion vector (209), and (9) a multiplexing unit that multiplexes 2FIi variable-length codes. It has exactly the same configuration as the conventional device shown in FIG.

(13) is a variable/fixed parallel converter that converts a multiplexed variable length code into a fixed bit width parallel signal;
4) is a transmission buffer that stores a fixed bit width parallel signal, and (15) is a parallel/serial converter that converts from a fixed bit width to 1 bit.

Next, the operation of the above embodiment will be explained. A quantized/coded signal (10B) subjected to variable length coding from an image input and a motion vector (110) subjected to variable length coding are transferred to a multiplexing unit (
The operation up to multiplexing in step 9) is the same as the conventional example shown in FIG.

Figure 2 shows a signal format diagram of the multiplexed signal (111) output from the multiplexer (9), and this figure shows the maximum value of the code length l (J: natural number) of the generated variable length code. An example in which Jmax is 4 is shown. Multiplexed signal (
111) is code length a and variable length code bO, bl, b2
．． b3, and the variable length code is literally variable length, so J! <、t! In the case of max, there are bits that have no meaning.

FIG. 3 is a block diagram showing the internal configuration of the variable length fixed parallel converter (13) to which the multiplexed signal (111) is input, and this figure shows that when a variable length code with a maximum code length of 1max is input This shows how the function of converting into a bit-parallel (l (: natural number) signal) is performed.

In Figure 3, (16) is an adder, (17) is a comparator that checks the magnitude relationship between the input value and k, (18) is a subtracter that performs the operation of (input value) -, and (19) is Addition signal (20
3) and the subtraction signal (204), and selector signal (2
06), (20) is a register for holding the previous value of residual code length, (21) is a selector for output signal, (22)
) is a selector for the remaining code, and (23) is a register for holding the previous value of the remaining code.

Assume that the code length input this time is 10, and the remaining code length up to the previous time was O.

The code length signal (201) is input to an adder (16) and is added to the previous remaining code length signal (202). Addition signal (
203) is input to the comparator (17) and compared with the value of k. J! Considering the case of Okk, (J!O+
0)<k is output as a comparison signal (205). When the addition signal (203) is smaller than k, the addition signal <203) itself is selected by the selector (19) and stored in the residual code length previous value holding register (20).

The input variable length code (210) is manually input to an output signal selector (21) and a residual code selector (22). In addition, the code length signal (201) and the residual code length signal (202) are input as control signals to both (21) and (22), and in this example, no output signal is selected and the residual code signal is used. The selector (22) uses a variable length code (21
0) is selected as is and the selector for holding the residual code previous value (
23). As a result of the above operation, a parallel signal of two bits will not be generated this time.

Next, assume that a variable length code (210) is input, and this code length signal (201) is 11. Remaining code length signal (20
2) J! 0 and 11 of the code length signal (201) are added to form an addition signal (203).

ノθ+J! Assuming that 1>k, the sum of the remaining code length up to the previous time and the current code length exceeds k, making it possible to generate a bit parallel signal. In this case, it is assumed that k is J1max5.

The output signal selector (22) outputs the residual code signal (211)
A parallel signal of bits is generated from the 10 bits of the current variable length code (210) and the (k-, &0) bits to be transmitted first among the 71 bits of the current variable length code (210) and output as an output signal.

The comparator (17) outputs a comparison result of JO+, Zl>k, which becomes an output strobe indicating the presence of an output signal. At the same time, the selector (19) uses the subtracter (18
) is selected and stored in the residual code length previous value holding register (20) as the residual code length.

In the residual code selector (21), the variable length code (210)
J! The remaining 1 bit output as an output signal,
! ! The 1-(klO) bit is selected and output as a residual code signal, and stored in the register (23) for holding the previous residual code value.

As described above, it is determined whether a k-bit parallel signal can be generated from the input variable length code, the residual code from the previous time, and each code length, and if it can be generated, the output signal and output cut lobe are used. Convert the variable-length parallel signal to a fixed-length parallel signal with a bit width of becomes possible.

The output signal (112) having a fixed width of k bits is written to the transmission buffer (14) using the output strobe as a control signal. If the transmission speed of the transmission line is fT (b/s), a signal is read out from the transmission buffer (14) at a speed of fT/k (b/s), and the signal is read out from the transmission buffer (14) at a speed of fT/k (b/s).
At step 15), the signal is converted into a serial signal and output onto the transmission line.

As explained above, according to the present invention, the processing of converting a variable length code into a bit parallel signal and writing to the transmission buffer are performed every time a variable length code is generated, even in the most frequent case. The processing speed does not need to exceed the pixel clock fO used in the explanation of the conventional example,
The read speed from the transmission buffer (14) is also realized at a clock speed of fT/.

As a result, even if the transmission speed fT of the transmission path is quite high, processing can be performed at a sufficiently low speed except for the fixed bit width parallel/serial converter (15) at the final stage, which allows the circuit size to be increased. There is no need to do so.

Furthermore, since parallel/serial conversion can be performed with a fixed width even in parts that move at high speed, it can be realized using small-scale and simple elements.

〔Effect of the invention〕

As described above, according to the present invention, a variable length code is converted into a parallel signal with a fixed bit width per unit without converting it into a serial signal, and is then converted into a serial signal directly transmitted to a transmission path. Therefore, even if the transmission path is high-speed,
The scale of the circuit that actually operates at high speed can be reduced, and the overall effect is that a compact and low-cost product can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an image encoding device according to an embodiment of the present invention, FIG. 2 is a format diagram of a multiplexed signal,
FIG. 3 is a block diagram showing the internal configuration of the variable/fixed parallel converter in the device of the present invention, FIG. 4 is a block diagram of a conventional image encoding device, and FIG. FIG. 2 is a diagram showing how information is generated. In the figure, (3) is a motion compensation prediction unit, (5) is a quantization/encoding unit, (8a) and (8b) are first and second variable length encoding units, and (9) is a multiplexing unit. , (13) is a variable/fixed parallel converter, (14) is a transmission buffer, and (15) is a parallel/serial converter. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Patent attorney Masuo Oiwa (2 others) Multiplexed signal format diagram Figure 2 Block 1 Block 2 Block 3 Block 4
Block 51 pixels Figure 5

Claims (1)

[Scope of Claims] A motion compensation prediction unit that inputs a digitized input image signal and an image signal of one frame before and outputs a motion vector and a predicted signal; an interframe subtracter that outputs an interframe difference signal; a quantization/encoding section that quantizes/encodes the interframe difference signal; and a quantization/encoding signal output from the quantization/encoding section. and first and second variable length encoding units that variable length encode the motion vector output from the motion compensation prediction unit; and variable length encoding and multiplexing in the first and second variable length encoding units. a variable/fixed parallel converter that converts the multiplexed signal into a parallel signal with a fixed bit width and stores it in a transmission buffer; and a parallel converter that converts the parallel signal with a fixed bit width reproduced from the transmission buffer into a serial signal. /A serial converter.