CN100433088C

CN100433088C - Driving circuit of display element, image display apparatus, and television apparatus

Info

Publication number: CN100433088C
Application number: CNB2005101199653A
Authority: CN
Inventors: 磯野青儿
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2004-06-30
Filing date: 2005-06-30
Publication date: 2008-11-12
Anticipated expiration: 2025-06-30
Also published as: CN1758306A

Abstract

A driving circuit for display elements, comprises a modulation circuit that outputs a modulating signal to be applied to wiring to which display elements are connected; and an output circuit that serializes modulation data including height value data for determining a height value of at least part of waveform of the modulating signal and pulse width data for determining a pulse width of at least part of waveform of the modulating signal so that the modulation data can be transmitted to the modulation circuit by transmission paths, the number of which is smaller than the number of bits of the modulation data, and outputs the serialized modulation data.

Description

The driving circuit of display element, image display device, television equipment

Technical field

The present invention relates to a kind of driving circuit of display element, particularly relate to brightness and make the luminous driving circuit of light-emitting component corresponding to gray-scale data.

Background technology

In as prior art patent document 1, put down in writing the driving method and the driving circuit that are used for constituting simply and at an easy rate driving circuit, this driving circuit is used for so that the stepped drive waveforms of pulse-length modulation and Modulation and Amplitude Modulation combination is come driven light-emitting element.

[patent documentation 1] spy opens 2003-316312 communique (with reference to Figure 12)

Summary of the invention

Be accompanied by the increase of gray shade scale number, the data line quantity of transmission will increase.For this reason, even the technology that also can suppress the increase of data line quantity under the situation that the gray shade scale number increases is developed in expectation solicitously.

Therefore, the purpose of this invention is to provide a kind of driving circuit that can realize that transmission path and transmission line quantity reduce.

The invention provides a kind of driving circuit that is used for display element, it is characterized in that, comprising: the modulation circuit of output modulation signal, this modulation signal are applied on the distribution that connects display element; Output circuit, it constitutes a plurality of transmission paths that lack by the bit number than modulating data the above-mentioned modulating data that contains crest value data and pulse width data is exported after with the mode serialization that can be transferred to above-mentioned modulation circuit, wherein, the crest value data are used to determine the crest value of at least a portion of the waveform of above-mentioned modulation signal; Pulse width data is used to determine the pulse width of at least a portion of the waveform of above-mentioned modulation signal, wherein, above-mentioned output circuit, on the transmission path of the regulation in above-mentioned a plurality of transmission paths, do not export serialized above-mentioned pulse width data and export serialized above-mentioned crest value data, in the transmission path of other in above-mentioned a plurality of transmission paths, do not export serialized above-mentioned crest value data and export serialized above-mentioned pulse width data.

An invention that the aspect is the driving circuit of following formation according to the application's invention.

That is:

A kind of driving circuit that is used for display element comprises:

The modulation circuit of output modulation signal, this modulation signal is applied to the distribution that connects display element;

Output circuit, it constitutes the transmission path that lacks by the bit number than above-mentioned modulating data and makes the modulating data that contains crest value data and pulse width data can be transferred to above-mentioned modulation circuit and make above-mentioned modulating data serialization and with its output, wherein the crest value data determine at least a portion crest value of the waveform of above-mentioned modulation signal, and pulse width data determines at least a portion pulse width of the waveform of above-mentioned modulation signal.

According to this structure, just can realize the reduction of transmission path quantity.

In this invention

Above-mentioned transmission path has many, can preferably adopt to constitute above-mentioned output circuit, so that

(i) in the above-mentioned transmission path of regulation, do not export serialized above-mentioned pulse width data and export serialized above-mentioned crest value data, in the above-mentioned transmission path of miscellaneous stipulations, do not export serialized above-mentioned crest value data and export serialized above-mentioned pulse width data; And

(ii) in the transmission path of the transmission path of afore mentioned rules or above-mentioned miscellaneous stipulations at least one the tunnel through in, in any one time in not transmitting data bit that constitutes above-mentioned crest value data and the data bit that constitutes above-mentioned pulse width data, export data bit arbitrarily;

Do not transmit data bit that constitutes above-mentioned crest value data and any one time that constitutes the data bit of above-mentioned pulse width data and be owing to the bit number (figure place) of the above-mentioned crest value data that are used to produce a modulation signal and be used to produce the time that the bit number of the above-mentioned pulse width data of this modulation signal does not match and produces.

According to this structure, just can improve the degree of freedom of the data setting when carrying out serialization.

In this invention, above-mentioned transmission path has many, constitutes above-mentioned output circuit, so that

(ii) in the transmission path of afore mentioned rules, in the time of not transmitting the data bit that constitutes above-mentioned crest value data, export data bit arbitrarily;

The time of not transmitting the data bit that constitutes above-mentioned crest value data is to be used to produce the time that the bit number of the above-mentioned pulse width data of this modulation signal does not match and produces the time owing to the bit number (figure place) of the above-mentioned crest value data that are used to produce a modulation signal;

Export above-mentioned data bit arbitrarily so that be positioned at identical position for constituting each data bit arrangement that respectively is worth mutually different a plurality of above-mentioned crest value data.

Perhaps

Can preferably adopt to constitute above-mentioned output circuit structure, so that

(ii) in the transmission path of above-mentioned miscellaneous stipulations, in the time of not transmitting the data bit that constitutes above-mentioned pulse width data, export data bit arbitrarily;

The above-mentioned time of not transmitting the data bit that constitutes above-mentioned pulse width data is owing to be used to produce the time that the bit number of the bit number of above-mentioned crest value data of a modulation signal and the above-mentioned pulse width data that is used to produce this modulation signal does not match and produces

Export above-mentioned data bit arbitrarily so that, be positioned at identical position for the arrangement that constitutes each data bit that respectively is worth mutually different a plurality of above-mentioned pulse width datas.

According to these structures,, also can in modulation circuit, easily carry out desired data regeneration even in the arrangement of data bit, insert under the situation of data bit arbitrarily.

Also have above-mentioned transmission path also to comprise the transmission path of at least a portion with at least a portion of the data bit that constitutes above-mentioned pulse width data of the data bit of transmitting the above-mentioned crest value data of formation simultaneously at least;

Above-mentioned modulation circuit can adopt such structure, promptly has:

Storage is via the memory circuit of the data bit of this transmission path,

In the data bit that reads the above-mentioned crest value data of formation from above-mentioned memory circuit and in, read data bit that constitutes above-mentioned pulse width data and the control circuit of exporting as pulse width data from above-mentioned memory circuit as the output of crest value data.

In addition, also can adopt such structure in this invention so that produce in serialization under the situation in non-transmission time of data owing to crest value data and pulse width data, same with foregoing invention, export data bit arbitrarily.

According to this structure, can make the data mixing parallel series transmission of different pieces of information character.

Particularly, in this structure, above-mentioned memory circuit has a plurality of memory elements of the data bit of storage input,

Above-mentioned a plurality of memory element is connected in series,

It is synchronous that each memory element constitutes and import new data bit, and the data bit that will import is input in the next memory element that is connected in series, and the new data bit of storage input,

Can suitably adopt such result, that is:

Output constitutes the data bit of above-mentioned crest value data from a part of memory element of these a plurality of memory elements that are connected in series, and output constitutes the data bit of above-mentioned pulse width data from the memory element of other parts.

In addition, in each above-mentioned invention, can suitably adopt such structure, promptly

Above-mentioned crest value data are data of crest value of part of the maximum crest value of the above-mentioned modulation signal of decision, and above-mentioned pulse width data is the pulse of the above-mentioned modulation signal of the decision data constantly that descend.

In addition, the application comprises the invention of image display device, and this image display device comes the display device of display image to constitute by above-mentioned driving circuit with according to the modulation signal from this driving circuit output.

In addition, the application comprises the invention of television equipment, and this television equipment constitutes by above-mentioned image display device and received television signal and with the receiving circuit that view data is supplied with this image display device.

Description of drawings

Fig. 1 is the block scheme according to the driving circuit of the first embodiment of the present invention.

Fig. 2 is the simple wiring diagram of expression according to the form of the modulation signal data that are input to the parallel/serial converted circuit in the modulation circuit of the first embodiment of the present invention.

Fig. 3 is the simple wiring diagram of expression according to the form of the serial data of the parallel/serial converted circuit output from modulation circuit of the first embodiment of the present invention.

Fig. 4 is the block diagram according to the modulation circuit in the driving circuit of the first embodiment of the present invention.

Fig. 5 is the block diagram according to the shift register in the modulation circuit of the first embodiment of the present invention.

Fig. 6 is the block diagram according to the pwm circuit in the modulation circuit of the first embodiment of the present invention.

Fig. 7 is the block diagram according to the output-stage circuit in the modulation circuit of the first embodiment of the present invention.

Fig. 8 is the oscillogram of expression according to an example of the output drive waveforms of the output-stage circuit in the modulation circuit of the first embodiment of the present invention.

Fig. 9 is the block diagram of the modulation circuit in according to a second embodiment of the present invention the driving circuit.

Figure 10 is a simple wiring diagram of representing the form of walking abreast from modulation circuit/serial data that the serial converted circuit is exported according to a second embodiment of the present invention.

Figure 11 is the block diagram of the shift register in the modulation circuit of driving circuit according to a second embodiment of the present invention.

Figure 12 is the block diagram according to television equipment of the present invention.

Embodiment

With reference to the accompanying drawings, exemplarily describe most preferred embodiment of the present invention in detail.But the size of Ji Zai component parts, material, shape and relative configuration thereof etc. in this embodiment are not confined to specific especially record, and it neither be intended to scope of the present invention is defined in this.In addition, in whole accompanying drawings of embodiment, identical or corresponding part is used identical symbol below.

(embodiment of television equipment)

At first, use Figure 12 to describe to going for television equipment of the present invention.Figure 12 is the block diagram according to television equipment of the present invention.Television equipment comprises set-top box (STB) 501 and image display device 502.

Set-top box (STB) 501 has receiving circuit 503 and I/F portion 504.Receiving circuit 503 is made of tuner and demoder etc., receiving satellite broadcast and by the TV signal of ripple on the ground etc., the data broadcasting of network etc., and decoded view data outputed to I/F portion 504.I/F portion 504 is transformed to view data the display format of image display device 502 and view data is outputed to image display device 502.

Image display device 502 has display panel 200, control circuit 505, driving circuit 506.Be included in control circuit 505 in the image display device 502 when the view data to input applies the Flame Image Process of the compensation deals that are adapted to display panel 200 etc., view data and various control signal are outputed to driving circuit 506.As an example, control circuit 505 has been enumerated the timing generation circuit 4 among Fig. 1.Driving circuit 506 outputs to display panel 200 with drive signal, and show television image on display panel 200 according to the view data of input.As an example, driving circuit 506 has been enumerated modulation circuit 2 and the sweep circuit 3 among Fig. 1.Display panel 200, for the following examples, as shown in Figure 1 exemplify out multichannel electron source 1.As multichannel electron source 1, for example can use the various display panels of FED, PDP, LCD display, LED, EL display etc.

In addition, receiving circuit 503 and I/F portion 504 promptly can be housed in the housing different with image display device 502 as set-top box (STB) 501, perhaps also can be housed in the identical housing with image display device 502.

At first, describe at driving circuit according to the display device of the first embodiment of the present invention.

Fig. 1 represents the driving circuit according to the first embodiment of the present invention.

Modulator approach as modulation signal can adopt pulse-length modulation that the time width value of modulation signal is modulated and the Modulation and Amplitude Modulation that the amplitude of modulation signal is modulated.If simple pulse-length modulation, the amplitude of establishing modulation signal is certain, and can be according to gray-scale data (wanting the data of the brightness that shows as expression, for example brightness data) decision pulse width.Also gray-scale data can be directly inputted to modulation circuit under this situation.In addition, if simple Modulation and Amplitude Modulation, the pulse width of establishing modulation signal is certain, and can determine amplitude according to gray-scale data.Also gray-scale data can be directly inputted to modulation circuit in this case.

On the other hand, the application's inventor is not to simple pulse-length modulation and simple Modulation and Amplitude Modulation, but studies at the structure of controlling two aspects according to the pulse width control and the amplitude of gray-scale data setting modulation signal.In this structure, in order to stipulate the pulse waveform of certain modulation signal, the suitable employing of modulation circuit has the structure of crest value initialization circuit and timing setting circuit, wherein the crest value initialization circuit is the circuit of crest value (amplitude) that is used to determine at least a portion of this modulation signal, and this timing setting circuit is the circuit of timing that is used to determine carry out the transition to from the crest value of at least a portion of this modulation signal other crest value (comprising the reference level (for example ground level etc.) by the benchmark of the amplitude of modulation signal).In such cases, with will have with the brightness of wanting to show one to one the gray-scale data of value of size be directly inputted to modulation circuit and compare, can suit to adopt and produce crest value data and timing data (carrying out the format conversion of gray-scale data) respectively, and these crest value data and timing data are input to the structure of modulation circuit, wherein the crest value data are with reference to the data of being set crest value by the crest value initialization circuit, and timing data is with reference to setting data regularly by the timing setting circuit.

Here among Shuo Ming the embodiment, describe at the most preferred embodiment under the situation that this crest value data and timing data is input to modulation circuit.

As shown in Figure 1, in the driving circuit of the 1st embodiment that multichannel electron source 1 is driven, have modulation circuit 2, sweep circuit 3, timing generation circuit 4, data conversion circuit 5, as the structure of parallel/serial converted circuit 6, multiple power supplies circuit 7 and the scanning power circuit 8 of output circuit.The part of the image displaying part in this driving circuit composing images display device.

Multichannel electron source 1 has the surface conductive type radiated element 1001 as display element.Though use surface conductive type radiated element as display element here, also can use various elements such as a type electronic emission element and electroluminescent cell as display element.In addition, using under the situation of electronic emission element as display element of surface conductive type radiated element etc., shine on the fluorophor luminous by the electronic emission element ejected electron.Come display image by this light.The brightness of light can be controlled by the exposure of the electronics of (among Biao Shi the embodiment, being in the selection cycle of a line sequential scanning here) in the stipulated time of electronic emission element.Control from size, the time-amplitude of voltage that the electron irradiation amount of electronic emission element can be by being applied to electronic emission element.The exposure that the application time of the modulation signal in during therefore, the potential difference (PD) of the current potential of current potential by the gated sweep signal and modulation signal and sweep signal apply can obtain expecting.

Multichannel electron source 1 can carry out that matrix driving has a plurality of scan wirings 1002 of connection like this and a plurality of modulation distribution 1003 makes to a plurality of display elements.At this scan wiring 1002 is applied said scanning signals, modulation distribution 1003 is applied modulation signal.

Modulation circuit 2 is connected the modulation distribution 1003 of multichannel electron source 1, the i.e. distribution of column direction.Be respectively that PHM data and pulse width data (timing data) are that the PWM data are input to this modulation circuit 2 with previously described crest value data.To carry out PHM data and the PWM data after the serial converted and be input to modulation circuit 2 by parallel/serial converted circuit 6 as output circuit.In addition, be the PWM data separately separately the time though the crest value data are PHM data and timing data, be not and the brightness that requires data one to one, can be by the modulation signal of the brightness that is used to by the modulation circuit generation with reference to two aspects realize requiring.Therefore, that is to say that the crest value data that are input to modulation circuit as modulating data are that PHM data and timing data are that the PWM data are the data that constitute corresponding to the gray-scale data of desired gray shade scale.Modulation circuit 2 is the circuit that produce modulation signal according to the modulating data of input.Modulation circuit 2 supplies to the column direction distribution that is connected with a plurality of electron sources respectively according to the modulation signal after will being modulated by the modulating data of parallel/serial converted circuit 6 inputs, thereby has the function as modulating device.

Sweep circuit 3 is connected the line direction distribution of multichannel electron source 1, and this sweep circuit 3 is to select signal (sweep signal) to supply with the circuit of scan wiring, and this scan wiring is connected the display element that can be driven by the output of modulation circuit 2.In general,, be not limited thereto inter-bank scanning and select multirow, also passable with planar selection multirow though what carry out is the line sequential scanning of selecting line by line.Promptly, sweep circuit 3, to the line direction distribution that connects as a plurality of electron sources that are included in the driven object in a plurality of electron sources in the multichannel electron source 1, supply with current potential at the appointed time, time beyond this stipulated time is supplied with non-selection current potential, thereby has the possibility of the selecting arrangement of the selection of going.

Timing generation circuit 4 is the circuit of timing signal that produce each circuit of modulation circuit 2, sweep circuit 3, data conversion circuit 5 and parallel/serial converted circuit 6.

Data conversion circuit 5 is to carry out will representing from the outside that the gray-scale data (brightness data) of the brightness that the multichannel electron source 1 from the outside requires is transformed to the circuit of the data conversion of the drive waveforms data layout that is adapted to modulation circuit 2.

Parallel/serial converted circuit 6 is that the parallel data that will be exported by data conversion circuit 5 is that gray-scale data is transformed to PHM data and PWM data, each parallel data is transformed to the circuit of serial data.Use Fig. 2 and Fig. 4 explanation be input in this parallel/serial converted circuit 6 data layout and by the data layout of parallel/serial converted circuit 6 outputs.

Fig. 2 represents to be input to the form of the drive waveforms data in parallel/serial converted circuit 6.This is the form of the data of data conversion circuit 5 outputs.As shown in Figure 2, these drive waveforms data are that shift clock 1 is synchronous with a timing signal that is produced by timing generation circuit 4, are to make PWM (Pulse WidthModulation) data parallel of the PHM (Pulse Height Modulation) of 2 bits and 10 bits respectively individually and the data layout that constitutes with respect to RGB.Promptly, in the state that is input to parallel/serial converted circuit 6, being used to produce the gray-scale data that is applied to corresponding to the modulation signal of the electronic emission element of the fluorophor that produces red light is 12 bit parallel data (the crest value data of 2 bits and the timing datas of 10 bits).Other color also is the same.That is, the data that are used to form a modulation signal pulse have that number is 12 side by side, the bit number of time series direction is 1 data layout in this grade.Here, though explanation is that the PHM data are 2 bits, the PWM data are the example of structure of 10 bits, might not be confined to such structure.

In addition, Fig. 3 represents the form by the drive waveforms data of parallel/serial converted circuit output.The hour hands signal that the drive waveforms data that Fig. 3 represents and timing generation circuit 4 produces is that shift clock 2 is synchronous, and these drive waveforms data are with PHM data and PWM data, respectively individually, and per 4 data layouts with data serializing.In addition, under the data conditions that has less than 4 bits, promptly produce under the situation in non-transmission time of data, output is as the virtual data of pseudo-data, so that the lack of fill part.As described later, in modulation circuit owing to constitute negligible virtual data, so can use arbitrarily data as virtual data.Specifically, can suit to adopt the signal level that will output in the transmission path forcibly to be defined as the structure of 0 level (low level) or 1 level (high level).

By this serialization, the also columns 12 of the parallel data of 12 bits (position) shown in Figure 2 reduces to and columns 4, and the bit number of time series direction (figure place) is increased to 4 from 1.Specifically, originally be 2 bit parallel data (and columns is 2, the bit number of time series direction be 1) the PHM data conversion for and columns is 1, the bit number of time series direction is 4 form.In addition, originally be 10 bit parallel data (and columns is 10, the bit number of time series direction be 1) the PWM data conversion for and columns is 3, the bit number of time series direction is 4 form.

Here, consider following conditions.Promptly

(1) condition that is not mixed in of so-called PHM data and PWM data

Satisfy under the situation of this condition,, produce and do not transmit data bit that constitutes the PHM data in the above-mentioned operable time or the time that constitutes the data bit of PWM data according to the bit number of PHM data and the bit number of PWM data.This is the time that the bit number owing to the bit number of PHM data and PWM data does not match and produces.

In addition, the illustrated embodiments for the embodiment that represents here constitutes satisfied two following conditions.Promptly

(2) condition is to equate with the operable time of time (being used for the time with 4 bit signal serial transmissions) that makes the PWM data that are used to form a modulation signal as transmission at another transmission path the operable time of time (being the time that is used for 4 bit signal serial transmissions here) that makes the PHM data that are used to form a modulation signal as transmission in a transmission path.

(3) condition is to make the transmission speed of each transmission path identical (bit number that time per unit can transmit).

If adopt this two conditions, just be difficult to eliminate by condition (1) producing, the above-mentioned time that does not match and produce owing to bit number.

Exist in when the signal level of transmission path becomes instability during this period of time and will produce the worry of misoperation.Therefore for present embodiment, export arbitrarily data (virtual data) in this time and eliminate this problem by constituting.

Specifically, adopt the structure that the PHM data of 2 bits are exported as the data of 4 bits.Here since the PHM data also can be appointed as 4 condition (specify here have modulation signal maximum crest value that become the condition of crest value), so 2 bits, promptly with 10 system methods, have 0,1,2,3 value.It is transformed to 4 bits.The data of 4 bits can be appointed as from 0 to 15 arbitrary value by 10 system methods.Therefore, original 4 values 0,1,2,3 can be transformed to 0 to 15 value arbitrarily and transmission.But, in order to pass through from the data of 4 bits, to take out 2 only specific Bit datas at the modulation electric trackside, formation can be reproduced the structure of original PHM data, preferably at 2 original Bit datas, promptly data bit is arbitrarily inserted in the identical position of " 00 ", " 01 ", " 10 ", " 11 ".Specifically, can adopt structure in the forward and backward or middle insertion data bit of the data of 2 bits.Also can use these insertion positions of combination as the situation of a plurality of data bit of insertion of present embodiment.For example, if insert conduct " 00 " of data bit arbitrarily before the data of 2 bits, so above-mentioned 4 values just become " 0000 ", " 0001 ", " 0010 ", " 0011 ".In such cases, for the modulation circuit that receives these data, can ignore 2 bits of first half.Owing to can ignore the data bit of insertion,, can adopt other data bit arbitrarily so need not to be " 00 ".In addition, also can adopt such structure: in the middle of 2 Bit datas, insert conduct " 1 " of data bit arbitrarily, insert " 0 " as the arbitrary data position at the end.In such cases, above-mentioned 4 values become " 0100 ", " 0110 ", " 1100 ", " 1110 ".For the modulation electric trackside, can reproduce 2 original bit PHM data by the bit of front and the bit of 3 bit numbers.

Also original 4 value 0,1,2,3 (10 system methods) can be replaced into from 0 to 15 value arbitrarily 7,8,9,10 (10 system method) and transmission.The signal of 4 bits becomes " 0111 ", " 1000 ", " 1001 ", " 1010 " in such cases, for only extracting 2 specific bits out, can not reproduce original PHM data.Therefore, for present embodiment, with respect to being worth (corresponding to the value of transmission state by resulting each of raw data.Owing to be with high level, 2 state transfer of low level here, be value with binary representation), be to have added the value of bit arbitrarily in identical position with the PHM data replacement, and with its transmission.Signal transmission state though suitable 2 values that adopt are transmitted (from the structure of high level and two states selections of low level transmission state), also can adopt other transmission states (for example, can select the structure of 4 transmission states).That is, data bit is not limited to 0 and 1.

The PWM data also are the same.As the PWM data conversion with 10 original bits is that 12 bits are (by transmission path serial transmission 4 bits.Owing to carry out this process, so become the data of 12 bits altogether by 3 transmission paths) transform method can adopt various transform methods.At the modulation electric trackside, in order to ignore specific bit and can to reproduce 10 original bit PWM data, for present embodiment, additional bit 12 arbitrarily compares specialization in 2 identical positions thereby can constitute all values with respect to original PWM data.

Multiple power supplies circuit 7 is the power circuits that can export a plurality of power values structures, is the circuit that is used to control modulation circuit 2.Though multiple power supplies circuit 7 is conventional voltage source circuits, might not be confined to this.

Scanning power circuit 8 is power circuits of a plurality of power values of output, is the circuit of gated sweep circuit 3.Though scanning power circuit 8 is conventional voltage source circuits, might not be confined to this.

Then, describe at modulation circuit 2.Fig. 4 represents the inner structure of modulation circuit 2.As shown in Figure 4, modulation circuit 2 constitute have shift register 9, pwm circuit 10 and output-stage circuit 11.

To carry out PHM serial data and the PWM serial data after the serial converted by serial translation circuit 6 and be input to shift register 9.In addition, utilize the modulating data of shift register 9 transmission, i.e. PHM parallel data and PWM parallel data corresponding to the column direction distribution of multichannel electron source 1.

From shift register 9, will be corresponding to the modulating data of the column direction distribution of multichannel electron source 1, promptly PHM parallel data and PWM parallel data are input to pwm circuit 10.And, by pwm circuit 10,, output-stage circuit 11 is exported being used to specify the output signal regularly of a plurality of signal levels (being equivalent to signal potential is crest value) of output-stage circuit 11 outputs.

In addition, be used to control the timing signal of shift register 9 and pwm circuit 10 by timing generation circuit 4 inputs.Output-stage circuit 11 is connected to multiple power supplies circuit 7, is the circuit that output has the modulation signal of drive waveforms described later.Fig. 5 represents the inner structure of shift register 9, Fig. 6 represents an example of the circuit structure that is equipped with on each bar column direction distribution as the pwm circuit shown in Fig. 4 10, an example of the circuit of each bar column direction distribution in the output-stage circuit 11 shown in Fig. 7 presentation graphs 4.

As shown in Figure 5, shift register 9 has the structure of a plurality of control circuits 12 and a plurality of memory circuit 13.In this first embodiment, though be to describe with the example of structure of using d type flip flop circuit, rest-set flip-flop circuit and AND circuit, control circuit 12 and memory circuit 13 are not limited thereto.

As shown in Figure 5, will carry out the PHM serial data after the serial converted and be input to the first memory circuit 13a by parallel/serial converted circuit 6.And by this first memory circuit 13a, transmission is corresponding to the modulating data of the column direction distribution of multichannel electron source 1, i.e. PHM parallel data.

To carry out the PWM serial data after the serial converted and be input to the second memory circuit 13b by parallel/serial converted circuit 6.In addition, though be called serial data here, this with respect to the data before the format conversion, carries out the serialization with respect at least a portion as so-called, and reduces the also data of columns, and columns is not limited to 1.In fact for the embodiment that illustrates here, the also columns of this PWM serial data is 3.Therefore, the second memory circuit 13b also is consistent with itself and columns, becomes 3 system configuration.But, become for fear of illustrating by Fig. 5 all and not know that the concentrated area represents this 3 system.By the modulating data of this second memory circuit 13b transmission corresponding to the column direction distribution of multichannel electron source 1, i.e. PWM parallel data.

In addition, a timing signal that will in timing generation circuit 4, produce, promptly be shifted trigger pulse and shift clock are input to control circuit 12.In addition, produce the modulating data that is used for corresponding to the column direction distribution of multichannel electron source 1, i.e. PHM serial data and the PWM data storage control signal in the first memory circuit 13a and the second memory circuit 13b by control circuit 12.

Storage control signal corresponding to this control circuit 12 produces when the PHM serial data being stored among the first memory circuit 13a, is stored in the PWM serial data among the second memory circuit 13b.

Constitute parallelly by the data of the first memory circuit 13a and second memory circuit 13b output, and, output to together in the pwm circuit 10 corresponding to the column direction distribution of multichannel electron source 1.

Specifically, the PWM serial data of the time series direction of 4 bits is transmitted in turn by 4 triggers of the second memory circuit 13b shown in Fig. 5.Be stored under the state of 4 triggers in PWM serial data,, export 4 bit parallel data by specifying output regularly with respect to trigger with this 4 bit time series direction.By carrying out this process respectively side by side, export the PWM parallel data of 12 bits by 3 systems.But because 2 bits are virtual datas, this virtual data can be out in the cold, in fact exports the PWM parallel data of 10 bits.

In addition, the PHM serial data with 4 time series direction is input to the first memory circuit 13a.But, because 2 in 4 are virtual datas, so memory circuit 13a is made of two triggers of 2 can storing except that virtual data.Thus, the PHM serial data is carried out parallelization.

Then, use Fig. 6, pwm circuit 10 is described.In addition, the pwm circuit 10 shown in Fig. 6 only is an example, might not be confined to the structure of this circuit.

As the embodiment that illustrates here, in the control of the amplitude direction that carries out modulation signal and two kinds of controls of control of time width direction, produce in the structure of modulation signal, can produce the modulation signal waveform of various complexity.For example, the unit interval (this is equivalent to constitute the one-period of the clock signal of counting object in by the structure of clock signal being counted the setting-up time width) that also can adopt the whole time width of the pulse that makes each modulation signal structure that produces corresponding to each unit interval of control wave peak-data separately.But need not to be the structure of this complexity.Specifically, as the crest value data, i.e. PHM data are so long as can stipulate that according to desired brightness the crest value information more at least in the waveform of a modulation signal is just passable.Specifically, as the information of regulation crest value more at least, can suit to adopt the information of specific maximum crest value in modulation signal.The size of crest value is not subjected to the restriction of the size of current potential in addition.For example, the selection current potential of sweep signal be than situation corresponding to the high current potential of the current potential of the conducting state of modulation signal under, the crest value of modulation signal, the side that current potential is low, it is big that the crest value of modulation signal becomes.

In addition, as timing data, be the PWM data, for example also can adopt the structure of information of each transit time of each crest value part (beginning to be used for time) of the waveform that all comprises the specified modulation signal from the status transition that is controlled to certain crest value to the control of another crest value.But need not to be the structure of this complexity.Specifically, as timing data, i.e. PWM data, can at least one position regulation to make the signal level of modulation signal carry out the transition to the information of time of other level by desired brightness just passable so long as contain.Specifically, in certain modulation signal, can suit to adopt use can stipulate that from the crest value that this modulation signal uses maximum crest value carries out the transition to the data of time of less crest value as the structure of timing data.The method of also with good grounds data stipulated time can adopt various structures.Employing can suit to adopt timing data to specify the structure of this timing time directly or indirectly to putting the structure that elapsed time carries out timing from reference time.Specifically timing can suit to adopt the structure of utilizing clock count.The appointment of timing time can be undertaken by specifying count value directly or indirectly under this situation.

According to the pwm circuit 10 of this first embodiment,, have PWM parallel data lock-in circuit 14 and PHM parallel data lock-in circuit 15 as lock-in circuit.In addition, at this pwm circuit 10, as with the circuit of enumeration correlation, be provided with counting circuit 16 sum counter rz signals and produce circuit 17.In addition, in this first embodiment, though use d type flip flop circuit and XOR circuit to know signal generating circuit 17 as counting, this circuit structure only is an example, might not be confined to this circuit structure.

In addition, pwm circuit 10, as decoding circuit, be provided with PHM data decode circuitry 18 and primary data signalization decoding circuit 19, as memory circuit, be provided with V1 and begin data storage circuitry 20, V2 and begin that data storage circuitry 21, V3 begin data storage circuitry 22, V4 begins data storage circuitry 23, V1 end data memory circuit 24, V2 end data memory circuit 25, V3 end data memory circuit 26 and V4 end data memory circuit 27.

In addition, pwm circuit 10, select circuit as end data, having the V1 end data selects circuit 28, V2 end data to select circuit 29, V3 end data to select circuit 30 and V4 end data to select circuit 31, as data comparison circuit, have V1 and begin that data comparator 32, V2 begin data comparator 33, V3 begins data comparator 34 and V4 begins data comparator 35, V1 end data comparer 36, V2 end data comparer 37, V3 end data comparer 38 and V4 end data comparer 39.

In addition, pwm circuit 10 produces circuit as pulse width, has the V1 pulse width and produces circuit 40, V2 pulse width circuit 41, V3 pulse width generation circuit 42 and V4 pulse width generation circuit 43.

Then, describe at the pwm circuit 10 of this first embodiment as constituted above.

At first, the PWM parallel data is the time that timing signal is an input signal that produces according to timing generation circuit 4 with lock-in circuit 14, and being used for the modulating data corresponding to the column direction distribution of the multichannel electron source 1 that is stored in the second memory circuit 13b in the shift memory 9 is the circuit that the PWM parallel data locks.

In addition, the PHM parallel data is the time that timing signal is an input signal that produces according to timing generation circuit 4 with lock-in circuit 15, and being used for the modulating data corresponding to the column direction distribution of the multichannel electron source 1 that is stored in the first memory circuit 13a in the shift memory 9 is the circuit that the PHM parallel data locks.

In addition, counter circuit 16 is a kind of like this circuit: its timing signal that produces according to timing generation circuit 4 is that PWM clock sum counter rz signal produces the counter rz signal that circuit 17 produces, and the enumeration data of regulation internal timing is outputed to V1 begin data comparator 32, V1 and begin data comparator 32, V2 and begin that data comparator 33, V3 begin data comparator 34, V4 begins data comparator 35, V1 end data comparer 36, V2 end data comparer 37, V3 end data comparer 38 and V4 end data comparer 39.

In addition, it is that a timing signal that is used for producing according to timing generation circuit 4 is input signal and PWM clock that the counter rz signal produces circuit 17, produces the circuit of the counter rz signal of regulation internal timing.

PHM data decode circuitry 18 is according to by the PHM parallel data of PHM parallel data with lock-in circuit 15 lockings, produces the V1 end data and selects circuit 28, V2 end data to select the decoding circuit of the selection signal of circuit 29 and V3 data selection circuit 30.

In this first embodiment, select signals according to 4 of the PHM parallel data generations of 2 bits.That is, under the situation of PHM data=" 00 ", the V1 end data selects the selection signal of circuit 28 to be input as " 1 ", and the selection signal of other selection circuit becomes " 0 ".Here " 00 " expression is by the numerical value of binary representation.In addition, under the situation of PHM data=" 01 ", the V2 end data selects the selection signal of circuit 29 to be input as " 1 ", and other select the selection signal of circuit to become " 0 ".In addition, under the situation of PHM data=" 10 ", the V3 end data selects the selection signal of circuit 30 to be input as " 1 ", and other select the selection signal of circuit to become " 0 ".Under the situation of PHM data=" 11 ", the V4 end data selects the selection signal of circuit 31 to be input as " 1 ", and other select the selection signal of circuit to become " 0 ".

In addition, primary data setting signal decoding circuit 19 in the pwm circuit 10 is such decoding circuits, it is according to a timing signal that produces in timing generation circuit 4, be the primary data setting signal, generation is used for and will begins data storage circuitry 20 with the PWM data storage that lock-in circuit 14 locks at V1 by the PWM parallel data, V2 begins data storage circuitry 21, V3 begins data storage circuitry 22, V4 begins data storage circuitry 23, V1 end data memory circuit 24, V2 end data memory circuit 25, V3 end data memory circuit 26, and the write signal in the V4 end data memory circuit 27.

In this first embodiment, select signals according to 8 of the primary data setting signal generations of 3 bits.

Promptly, under the situation of primary data setting signal=" 000 ", the write signal that only V1 is begun data storage circuitry 20 becomes conducting, will specify beginning to begin in the data storage circuitry 20 to being stored in V1 by the PWM parallel data with the data (V1 begins data: this is by giving the time appointment that obtains data in advance with PWM data same paths) of crest value transition (increasing the transition of the crest value direction) position of the V1 of lock-in circuit 14 lockings.

Under the situation of primary data setting signal=" 001 ", the write signal that only V2 is begun data storage circuitry 21 becomes conducting, will specify beginning to begin in the data storage circuitry 21 to being stored in V2 by the PWM parallel data with the data (V2 begins data: this is by giving the time appointment that obtains data in advance with PWM data same paths) of crest value transition (increasing the transition of the crest value direction) position of the V2 of lock-in circuit 14 lockings.

Under the situation of primary data setting signal=" 010 ", the write signal that only V3 is begun data storage circuitry 22 becomes conducting, will specify beginning to begin in the data storage circuitry 22 to being stored in V3 by the PWM parallel data with the data (V3 begins data: this is by giving the time appointment that obtains data in advance with PWM data same paths) of crest value transition (increasing the transition of the crest value direction) position of the V3 of lock-in circuit 14 lockings.

Under the situation of primary data setting signal=" 011 ", the write signal that only V4 is begun data storage circuitry 23 becomes conducting, will specify beginning to begin in the data storage circuitry 23 to being stored in V4 by the PWM parallel data with the data (V4 begins data: this is by giving the time appointment that obtains data in advance with PWM data same paths) of crest value transition (increasing the transition of the crest value direction) position of the V4 of lock-in circuit 14 lockings.

Under the situation of primary data setting signal=" 100 ", only the write signal with V1 end data memory circuit 24 becomes conducting, and appointment is begun from being stored in the V1 end data memory circuit 24 to the data (the V1 end data: this is by giving the time appointment that obtains data in advance with PWM data same paths) of lower crest value crossover position by the V1 of PWM parallel data with lock-in circuit 14 lockings.

Under the situation of primary data setting signal=" 101 ", only the write signal with V2 end data memory circuit 25 becomes conducting, and appointment is begun from being stored in the V2 end data memory circuit 25 to the data (the V2 end data: this is by giving the time appointment that obtains data in advance with PWM data same paths) of lower crest value crossover position by the V2 of PWM parallel data with lock-in circuit 14 lockings.

Under the situation of primary data setting signal=" 110 ", only the write signal with V3 end data memory circuit 26 becomes conducting, and appointment is begun from being stored in the V3 end data memory circuit 26 to the data (the V3 end data: this is by giving the time appointment that obtains data in advance with PWM data same paths) of lower crest value crossover position by the V3 of PWM parallel data with lock-in circuit 14 lockings.

Under the situation of primary data setting signal=" 111 ", only the write signal with V4 end data memory circuit 27 becomes conducting, and appointment is begun from being stored in the V4 end data memory circuit 27 to the data (the V4 end data: this is to give the time appointment that obtains data in advance by PWM data same paths) of lower crest value crossover position by the V4 of PWM parallel data with lock-in circuit 14 lockings.

In the data storage circuitry 20～27 of these starting position specific datas of storage and end position specific data, at the image that contains device when starting in the non-display cycle, sequentially transmit the above-mentioned parameter that is used to form drive waveforms (V1 begin data, V2 begin data, V3 begin data, V4 begins data, V1 end data, V2 end data, V3 end data and V4 end data).Thus, stored parameter (V1 begin data, V2 begin data, V3 begin data, V4 begins data, V1 end data, V2 end data, V3 end data and V4 end data) in data storage circuitry 20～27.

In addition, the V1 end data in the pwm circuit 10 select circuit 28 be to by the PWM parallel data with the PWM data of lock-in circuit 14 lockings be stored in any one selection circuit of selecting in the V1 end data in the V1 end data memory circuit 24.This selection is by realizing according to the selection signal of the PHM data of exporting from PHM data decode circuitry 18.

In addition, it is by according to the selection signal from the PHM data of PHM data decode circuitry 18 outputs that the V2 end data is selected circuit 29, to by the PWM parallel data with the PWM data of lock-in circuit 14 lockings be stored in any one selection circuit of selecting in the V2 end data in the V2 end data memory circuit 25.

Similarly, it is by according to the selection signal from the PHM data of PHM data decode circuitry 18 outputs that the V3 end data is selected circuit 30, to by the PWM parallel data with the PWM data of lock-in circuit 14 lockings be stored in any one selection circuit of selecting in the V3 end data in the V3 end data memory circuit 26.

In addition, similarly, it is by according to the selection signal from the PHM data of PHM data decode circuitry 18 outputs that the V4 end data is selected circuit 31, to by the PWM parallel data with the PWM data of lock-in circuit 14 lockings be stored in any one selection circuit of selecting in the V4 end data in the V4 end data memory circuit 26.

It is under the situation of " 1 " selecting signal that V1 selects circuit to the V4 end data, selects the PWM data, is under the situation of " 0 " selecting signal, selects to be stored in the end data in the corresponding end data memory circuit.

In addition, to begin data comparator 32 be to be used for beginning the enumeration data of counting circuit 16 of data and regulation internal timing and producing the comparer that V1 begins pulse when consistent when being stored in V1 that V1 begins data storage circuitry 20 to V1.It is to be used for beginning the enumeration data of data and counting circuit 16 and producing the comparer that V2 begins pulse when consistent when being stored in V2 that V2 begins data storage circuitry 21 that V2 begins data comparator 33.It is to be used for beginning data storage circuitry 22 V3 and beginning the enumeration data of counting circuit 16 of data and regulation internal time and produce the comparer that V3 begins pulse when consistent when being stored in V3 that V3 begins data comparator 34.It is to be used for beginning data storage circuitry 23 V4 and beginning the enumeration data of counting circuit 16 of data and regulation internal time and produce the comparer that V4 begins pulse when consistent when being stored in V4 that V4 begins data comparator 35.

In addition, V1 end data comparer 36 is to produce the comparer that V1 finishes pulse when the enumeration data of the V1 end data of being selected circuit 28 to select by the V1 end data or PWM data and counting circuit 16 is consistent.V2 end data comparer 37 is to produce the comparer that V2 finishes pulse when the enumeration data of the V2 end data of being selected circuit 29 to select by the V2 end data or PWM data and counting circuit 16 is consistent.V3 end data comparer 38 is to produce the comparer that V3 finishes pulse when the enumeration data of the V3 end data of being selected circuit 30 to select by the V3 end data or PWM data and counting circuit 16 is consistent.V4 end data comparer 39 is to produce the comparer that V4 finishes pulse when the enumeration data of the V4 end data of being selected circuit 31 to select by the V4 end data or PWM data and counting circuit 16 is consistent.

In addition, V1 pulse width generation circuit 40 is pwm circuits of output pulse width waveform TV1.Pulse width waveform TV1 begins V1 that pulse is risen, that produce at the V1 that V1 begins to produce in the data comparator 32 to finish the waveform that pulse descends in V1 end data comparer 36.

In addition, V2 pulse width generation circuit 41 is pwm circuits of output pulse width waveform TV2.Pulse width waveform TV2 begins V2 that pulse is risen, that produce at the V2 that V2 begins to produce in the data comparator 33 to finish the waveform that pulse descends in V2 end data comparer 37.

In addition, V3 pulse width generation circuit 42 is pwm circuits of output pulse width waveform TV3.Pulse width waveform TV3 begins V3 that pulse is risen, that produce at the V3 that V3 begins to produce in the data comparator 34 to finish the waveform that pulse descends in V3 end data comparer 38.

In addition, V4 pulse width generation circuit 43 is pwm circuits of output pulse width waveform TV4.Pulse width waveform TV4 begins V1 that pulse is risen, that produce at the V4 that V4 begins to produce in the data comparator 35 to finish the waveform that pulse descends in V4 end data comparer 39.

In addition, in this first embodiment,, in the rest-set flip-flop circuit, be input to the set input,, might not be confined to this structure finishing the circuit that pulse is input to the input that resets though employing will begin pulse as pwm circuit.

In addition, as shown in Figure 7, current potential V1～V4 is 0＜V1＜V2＜V3＜V4, corresponds respectively to PWM output waveform TV1, TV2, and TV3 and TV4 are exported.In addition, transistor Q1, Q2, Q3 and Q4 constitute and can respectively current potential V1～V4 be outputed to the structure of lead-out terminal OUTPUT by making their conductings.In addition, for transistor Q1～Q4, also can constitute by bipolar transistor.

Then, with reference to Fig. 8 explanation drive waveforms from the lead-out terminal OUTPUT output of the modulation circuit 2 that constitutes as mentioned above.

Fig. 8 A is illustrated under the situation of PHM data=" 11 ", uses the drive waveforms of current potential V1～V4.Shown in Fig. 8 A, the rising edge position of current potential V1 begins V1 in the data storage circuitry 20 and begins data and stipulate by being stored in V1.In addition, the rising edge position of current potential V2 begins V2 in the data storage circuitry 21 and begins data and stipulate by being stored in V2.In addition, the rising edge position of current potential V3 begins V3 in the data storage circuitry 22 and begins data and stipulate by being stored in V3, and the rising edge position of current potential V4 begins the data regulation by being stored in the V4 that V4 begins in the data storage circuitry 23.

On the other hand, the negative edge position of current potential V1 is stipulated that by the V1 end data that is stored in the V1 end data memory circuit 24 the negative edge position of current potential V2 is stipulated by the V2 end data that is stored in the V2 end data memory circuit 25.In addition, the negative edge position of current potential V3 is stipulated that by the V3 end data that is stored in the V3 end data memory circuit 26 the negative edge position of current potential V4 is stipulated by the V4 end data that is stored in the V4 end data memory circuit 27.

Fig. 8 B is illustrated under the situation of PHM data=" 10 ", arrives the drive waveforms of using before current potential V1～V3.

Shown in Fig. 8 B, the rising edge position of current potential V1 begins V1 in the data storage circuitry 20 and begins data and stipulate by being stored in V1, and the rising edge position of current potential V2 begins V2 in the data storage circuitry 21 and begins data and stipulate by being stored in V2.In addition, the rising edge position of current potential V3 begins V3 in the data storage circuitry 22 and begins data and stipulate by being stored in V3.

On the other hand, the negative edge position of current potential V1 is stipulated that by the V1 end data that is stored in the V1 end data memory circuit 24 the negative edge position of current potential V2 is stipulated by the V2 end data that is stored in the V2 end data memory circuit 25.In addition, the negative edge position of current potential V3 is stipulated by the PWM data.

In addition, Fig. 8 C is illustrated under the situation of PHM data=" 01 ", uses the drive waveforms of current potential V1 and V2.

Shown in Fig. 8 C, the rising edge position of current potential V1 begins V1 in the data storage circuitry 20 and begins data and stipulate by being stored in V1, the rising edge position of current potential V2 begins V2 in the data storage circuitry 21 and begins data and stipulate by being stored in V2, the negative edge position of current potential V1 is decided by V1 end data rule the coming that is stored in the V1 end data memory circuit 24, and the negative edge position of current potential V2 is stipulated by the PWM data.

Fig. 8 D is illustrated under the situation of PHM data=" 01 ", uses the drive waveforms of current potential V1.Shown in Fig. 8 D, the rising edge position of current potential V1 begins V1 in the data storage circuitry 20 and begins data and stipulate that the negative edge position of current potential V1 is stipulated by the PWM data by being stored in V1.

As from as can be known above-mentioned, in the present embodiment, become corresponding to the modulation signal of each gray-scale data, by the pulse width of the part of each maximum crest value control by the timing data that constitutes gray-scale data (PWM data) decision (modulation).The shape of other parts of each modulation signal (by the part beyond the part of maximum crest value control) can begin data, V2 by V1 and begin data, V3 and begin data, V4 and begin data, V3 end data, V2 end data, V1 end data and decide according to gray-scale data.But, be not limited to this structure according to which pulse width partly of gray-scale data decision modulation signal.For present embodiment, in the modulation signal that uses second later crest value (being equivalent to above-mentioned V2, V3, V4), in the rising edge part and negative edge part of modulation signal, crest value does not directly rise to maximum crest value this modulation signal from reference level, and through the intermediate wave peak value.Can suppress thus owing to applying the vibration that modulation signal produces.Specifically the rising edge of modulation signal part and negative edge partly constitute stairstepping, and this can begin data, V3 and begin data, V4 and begin data, V3 end data, V2 end data, V1 end data and set the timing that obtains stairstepping for and realize by V1 being begun data, V2.

As described above, driving circuit according to the display element of this first embodiment, the transmission path (transmission line) that lacks by the bit number that utilizes than the data bit of formation PWM data and PHM data makes it serialization with PWM data and PHM data transmission to modulation circuit 2, not quite amplitude increases the transmission line number in the structure and transmits two kinds of data with different attribute thus, and this different attribute is to be used to carry out and with the modulation of Modulation and Amplitude Modulation and pulse-length modulation.

Particularly for this embodiment, even in gray-scale data any one path from parallel/serial converted circuit transmission to the transmission path of modulation circuit, also do not make the different data of attribute, promptly crest value data and timing data are mixed.For this reason, with gray shade scale from parallel/serial converted circuit transmission after modulation circuit, also can not be provided for separating the structure of crest value data and timing data, reset but have.

(second embodiment)

Then, describe at the second embodiment of the present invention.In addition, the summary of the driving circuit of this second embodiment is identical with first embodiment.Promptly, as shown in Figure 1, having the structure of modulation circuit 2, sweep circuit 3, timing generation circuit 4, data conversion circuit 5, parallel/serial converted data 6, multiple power supplies circuit 7 and scanning power circuit 8 according to the drive unit of this second embodiment, is the circuit that drives multichannel electron source 1.

In addition, sweep circuit 3 is the circuit that are connected on the line direction distribution of multichannel electron source 1, are used to select whether the output of modulation circuit 2 is supplied with any delegation signal of multichannel electron source 1.And, in general,, needn't necessarily be confined to the line sequential scanning though carry out the line sequential scanning that sequential lines that delegation meets delegation is selected, also can be inter-bank scanning and select a plurality of row simultaneously, or be chosen as planar.Promptly, sweep circuit 3 is to supply with the stipulated time by the line direction distribution that a plurality of electron sources that become the driven object in a plurality of electron sources that are included in the multichannel electron source 1 are connected to select current potential, and supplies with the selecting arrangement of the capable selection of non-selection current potential at other times.In addition, because identical among the circuit structure beyond the modulation circuit 2 that the following describes and the peripheral circuits of this modulation circuit 2 being supplied with serial datas and first embodiment, so omission is to its explanation.

Then, describe at the modulation circuit 2 of the second embodiment of the present invention and the supply of serial data.Fig. 9 represents the inner structure of modulation circuit 2 and the peripheral circuits that serial data is supplied to modulation circuit 2.As shown in Figure 9, the modulation circuit 2 of this second embodiment is identical with first embodiment, also has the structure of shift register 9, pwm circuit 10 and output-stage circuit 11.In addition, output-stage circuit 11 is to be connected multiple power supplies circuit 7, is used to export the circuit of the modulation signal with drive waveforms described later.

Data conversion circuit 5 is the circuit that are used to carry out from the outside brightness level data of the brightness grade control of multichannel electron source 1 is transformed to the data conversion of the drive waveforms data layout that is applicable to modulation circuit 2.

Parallel/serial converted circuit 6 be with PHM data and PWM data in the attribute of any one data irrelevant, to use as parallel data without exception from the brightness level data that data conversion circuit 5 is supplied with, and this parallel data will be transformed to the circuit of serial differential data.For this second embodiment, though describe as an example, might not be confined to differential data with the situation of differential data, specifically, for example also can utilize single end data and pseudo-differential data etc.

Then, use Fig. 2 and Figure 10, the data layout in/serial converted circuit 6 parallel and describe from the data layout of parallel/serial converted circuit 6 outputs to being input to.In addition, owing to the form of the drive waveforms data that are input to parallel/serial converted circuit is identical with first embodiment, so omit to its explanation.Figure 10 represents from the form of the drive waveforms data of the parallel/serial converted circuit output of present embodiment.

That is, as shown in Figure 2, the drive waveforms data of second embodiment are identical with first embodiment, and the drive waveforms data of this second embodiment are by RGB, the data layout that the PWM data parallel with the PHM data of 2 bits and 10 bits of distributing individually constitutes.And, these drive waveforms data and a timing signal that supplies to data conversion circuit 5 from timing generation circuit 4, promptly shift clock 1 is synchronous.In addition, in this second embodiment, though be to be 2 bits with the PHM data, the PWM data are that the situation of 10 bits describes as an example, might not be confined to 10 bits, also can adopt bit number in addition.

As shown in figure 10, the serial data of this second embodiment and a timing signal that produces by timing generation circuit 4, be that shift clock 2 is synchronous, the attribute of any one so-called data in itself and PHM data and the PWM data is irrelevant, be to make data, carry out serialized data layout with per 4 as data.In addition, for this second embodiment, in two edges of the rising edge of shift clock and negative edge,, might not be confined to this structure though adopt the structure that becomes by triggering.And, for this second embodiment, though data bits is the value (can by 4 values of removing) of 4 multiple, but under data bits can not be by 4 situations about removing, promptly under the situation that produces the non-transmission time of data, fill virtual data, and output to the data of 4 of less thaies as pseudo-data.

In addition, as shown in Figure 9, modulation circuit 2 is connected the column direction distribution of multichannel electron source 1.This modulation circuit 2 is according to by parallel/serial converted circuit 6 is unified PHM data and PWM data being carried out modulating data (gray-scale data) after the serial converted, being used for modulation signal is supplied with the circuit of multichannel electron source 1.That is, this modulation circuit 2 has according to the modulating data from parallel/serial converted circuit 6 inputs, the modulation signal after the modulation is supplied with the function of the modulating device of the column direction distribution that is connected with a plurality of electron sources respectively.

Then, describe at the shift register 9 in the modulation circuit 2 that is arranged on this second embodiment.Figure 11 represents the inner structure of the shift register 9 of this second embodiment.

As shown in figure 11, carried out PHM serial data and the PWM serial data after the serial converted in shift register 9 inputs of this second embodiment by parallel/serial converted circuit 6.In addition, from the modulating data of shift register 9 outputs corresponding to the column direction distribution of multichannel electron source 1, i.e. PHM parallel data and PWM parallel data.As shown in figure 10, the employed data of modulation signal that will be used between a selection cycle display element of modulation in generation as and the parallel data of columns 12 be input to parallel/serial converted circuit 6, parallel serial conversion for and columns is 3, the form of the bit number 4 of time series direction.That is, in shift register shown in Figure 11 9 input as the signal of 3 systems (and columns is 3) of serial data.

To supply to pwm circuit 10 as the PHM parallel data and the PWM parallel data of the modulating data of exporting from shift register 9.This pwm circuit 10 is in output-stage circuit 11, is used to produce the circuit according to the output of each output voltage.In addition, supply with the timing signal that is used to control shift register 9 and pwm circuit 10 from timing generation circuit 4.

In addition, as shown in figure 11, the shift register 9 of this second embodiment is configured to have a plurality of control circuits 52 and a plurality of memory circuit 53.In addition, in this second embodiment,, might not be confined to such circuit structure though describe as an example with the situation of using d type flip flop circuit, rest-set flip-flop circuit and OR circuit to constitute control circuit 52 and memory circuit 53.

Memory circuit 53a, memory circuit 53b, memory circuit 53c constitute the circuit that each serialized 3 system data is transformed to parallel data.In memory circuit 53b, memory circuit 53c, import the unmixed 2 system's serial datas of PHM data and PWM data respectively.Serial data is by memory element, and promptly trigger transmits, and timing is in accordance with regulations exported as parallel data.In memory circuit 53a input, comprise by in the parallel/PHM data after serial converted circuit 6 is unified to carry out serial converted and the serial data of PWM data, particularly the data of PHM data and PWM data serial mixing.Memory circuit 53a be connected in series 4 memory elements, i.e. triggers.Each trigger is in the data bit of storage input, and input is stored in the serial data in the next stage trigger.The serial data that keeps 4 bits by these four triggers.2 Bit datas are wherein exported as the PHM data, 2 other bits are exported as the PWM data.2 bit PWM data of memory circuit 53a output constitute the PWM parallel data of 10 bits with 4 bit PWM data of 4 bit PWM data of memory circuit 53b output and memory circuit 53c output.Thus, will be corresponding to the modulating data of the column direction distribution of multichannel electron source 1, promptly PHM parallel data and PWM parallel data output to pwm circuit 10.

In addition, will be by a timing signal of timing generation circuit 4 generations, i.e. displacement beginning pulse and shift clock supply to control circuit 52.This control circuit 52 is the circuit that produce control signal, and this control signal is used for the modulating data corresponding to the column direction distribution of multichannel electron source 1, and promptly PHM serial data and PWM uniform data are stored in the memory circuit 53.Here, shift pulse is a timing signal that produces by in timing generation circuit 4, the clock that promptly differential shift clock forms.And, can adopt the structure of transmission data in the time at two edges of the rising edge of this clock and negative edge.

And the storage control signal according to being produced by control circuit 52 is stored in serial data in the memory circuit 53.Constitute parallel data from the output data of memory circuit 53 outputs.Column direction distribution according to multichannel electron source 1 together supplies to pwm circuit 10 with this output data.

As mentioned above, constitute the driving circuit of the display element of this second embodiment.

Driving circuit according to the image display device of this second embodiment, can obtain with the same effect of first embodiment in, even little amplitude increases the transmission line number in the structure, the data of 2 kinds of attributes of also can transmit dual-purpose Modulation and Amplitude Modulation and pulse-length modulation.Particularly in a second embodiment, the memory circuit by constituting output wave peak-data and timing data respectively is so that have modulation circuit, so crest value data and timing data are mixed and make it serialization.Thus, do not need virtual data, perhaps can reduce essential virtual data.

Though more than be that the present invention is not limited to the foregoing description to the specifying of the embodiment of the invention, according to the thought of technology of the present invention various distortion can be arranged.

For example, the structure of the pwm circuit of enumerating in the above-described embodiments, shift register, output-stage circuit, PHM data and PWM data is example only, also can adopt different therewith structures as required.

In sum, according to the present invention, by making the crest value data bit and the pulse width data bit serialization of the modulation signal that determines modulating wave peak value and pulse width, can realize the reduction of transmission path and transmission line quantity, so even under the situation that increases gray shade scale quantity, also can suppress the increase of the data line quantity that is used to transmit.

Claims

1. a driving circuit that is used for display element is characterized in that, comprising:

The modulation circuit of output modulation signal, this modulation signal are applied on the distribution that connects display element;

Output circuit, it constitutes a plurality of transmission paths that lack by the bit number than modulating data the above-mentioned modulating data that contains crest value data and pulse width data is exported after with the mode serialization that can be transferred to above-mentioned modulation circuit, wherein, the crest value data are used to determine the crest value of at least a portion of the waveform of above-mentioned modulation signal; Pulse width data is used to determine the pulse width of at least a portion of the waveform of above-mentioned modulation signal,

Wherein, above-mentioned output circuit, on the transmission path of the regulation in above-mentioned a plurality of transmission paths, do not export serialized above-mentioned pulse width data and export serialized above-mentioned crest value data, in the transmission path of other in above-mentioned a plurality of transmission paths, do not export serialized above-mentioned crest value data and export serialized above-mentioned pulse width data.

2. driving circuit according to claim 1 is characterized in that:

Above-mentioned output circuit constitutes that whether on the transmission path afore mentioned rules or not transmission constitute the time of the data bit of above-mentioned crest value data, transmission did not constitute in time of data bit of above-mentioned pulse width data on above-mentioned other transmission path, exported data bit arbitrarily;

Wherein, the above-mentioned time is the time that the bit number owing to the bit number of the above-mentioned crest value data that are used to produce a modulation signal and the above-mentioned pulse width data that is used to produce this modulation signal does not match and produces.

3. driving circuit according to claim 1 is characterized in that:

Whether above-mentioned output circuit constitute on the transmission path afore mentioned rules or not transmission and be used to constitute in time of data bit of above-mentioned crest value data, exports data bit arbitrarily;

Wherein, the time of not transmitting the data bit that constitutes above-mentioned crest value data is owing to be used to produce the time that bit number that the bit number and being used to of the above-mentioned crest value data of a modulation signal produces the above-mentioned pulse width data of this modulation signal does not match and produces;

Export above-mentioned data bit arbitrarily, make it be positioned at identical position with respect to the arrangement that constitutes each data bit that respectively is worth mutually different a plurality of above-mentioned crest value data.

4. driving circuit according to claim 1 is characterized in that:

Above-mentioned output circuit constitute or not on above-mentioned other the transmission path transmission constitute in time of data bit of above-mentioned pulse width data, export data bit arbitrarily;

Wherein, the time of not transmitting the data bit that constitutes above-mentioned pulse width data is owing to be used to produce the time that bit number that the bit number and being used to of the above-mentioned crest value data of a modulation signal produces the above-mentioned pulse width data of this modulation signal does not match and produces

Export above-mentioned data bit arbitrarily, make it be positioned at identical position with respect to the arrangement that constitutes each data bit that respectively is worth mutually different a plurality of above-mentioned pulse width datas.

5. driving circuit according to claim 1 is characterized in that,

Above-mentioned modulation circuit has:

Be used to store via the memory circuit of the data bit of above-mentioned a plurality of transmission path and

When from above-mentioned memory circuit, reading the data bit that constitutes above-mentioned crest value data and exporting, also from above-mentioned memory circuit, read the control circuit that the data bit that constitutes above-mentioned pulse width data is exported as pulse width data as the crest value data.

6. driving circuit according to claim 5 is characterized in that,

Above-mentioned memory circuit has a plurality of memory elements of the data bit that storage imports,

Above-mentioned a plurality of memory element is connected in series,

Each memory element constitutes: synchronous with the new data bit of input, data bit stored is input in the next memory element that is connected in series, and the new data bit imported of storage,

A part of memory element output from a plurality of memory elements that this is connected in series constitutes the data bit of above-mentioned crest value data, and exports the data bit that constitutes above-mentioned pulse width data from other memory element.

7. driving circuit according to claim 1 is characterized in that, above-mentioned crest value data are the data of crest value of a part that are used to determine the maximum crest value of above-mentioned modulation signal.

8. driving circuit according to claim 1 is characterized in that, above-mentioned pulse width data is the pulse decline data constantly that are used to determine above-mentioned modulation signal.

9. image display device, its feature in, comprising:

Any described driving circuit in the claim 1 to 8; And

Come the display device of display image according to modulation signal by this driving circuit output.

10. a television equipment is characterized in that, comprising:

The described image display device of claim 9; And

Received television signal also offers view data the receiving circuit of this image display device.