JPH09200058A - Data converter and its method, and data transmitter and pulse width modulator using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of circuits for high speed pulse width modulation(PWM) by adopting the configuration for parallel serial/serial parallel conversion to PWM processing in an image processing unit. SOLUTION: A recovered clock signal whose duty is 50% of that of a clock signal in input data is generated, a triangle wave section 7 generates a triangle wave signal synchronously with the recovered clock signal, comparators 8-14 generates plural reference signals based on the triangle wave signal, and a data conversion section 19 executes serial parallel conversion or parallel serial conversion selectively based on an S/P signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion device and a method thereof, for example, a parallel-serial conversion and a data conversion device and method for performing serial-parallel conversion. The present invention also relates to a data transmission device and a pulse width modulation device using the data conversion device and the method.

[0002]

2. Description of the Related Art FIG. 10 shows a schematic configuration of a conventional data transmission system for performing serial data transmission. For example, on the transmission side, the parallel-serial conversion unit 64 converts 8-bit parallel data into 8-bit serial data. Hereinafter, this conversion operation is referred to as "Parasili conversion". Then, the converted serial data, its converted clock signal, and the LOAD signal of one cycle of 8-bit serial data are transmitted to the receiving side. On the receiving side, the serial / parallel converter 65
The 8-bit serial data received in step 2 is converted into 8-bit parallel data. Hereinafter, this operation will be referred to as Silipara conversion.

Next, FIG. 11 shows a detailed configuration of the parallel-serial conversion unit 64 described above. The parallel-serial converter 64 includes seven switches (SW) 74 to 80 and eight Ds as shown in FIG.
It is composed of flip-flops (DFF) 66 to 73.

In FIG. 11, the data input terminal of DFF 66 is connected to DP1 which is the LSB of parallel image data, and the output of DFF 66 is connected to one of the input terminals of SW74. Parallel image data DP2 is input to the other input terminal of SW74, and SW74
The output of is connected to the data input terminal of the DFF 67. The output of the DFF 67 is connected to one of the input terminals of the SW75, and the parallel image data DP3 is input to the other input terminal of the SW75. The output of SW75 is connected to the data input terminal of DFF68.
Then, the above configuration is repeated up to the DFF 73.

A conversion clock CK is similarly connected to the clock input terminals of the DFFs 66 to 73. Here, the conversion clock CK has a frequency that is eight times the pixel clock frequency. The parallel image data DP8 to DP1 are
It is updated in pixel clock cycle units.

Further, the LOAD signal acting as a selection signal for the SWs 74 to 80 is at the "L" level only for one conversion clock (CK) cycle from the change point of the image data. S
W74 to W80 select the input on the upper side (● side) in the figure while the LOAD signal is at the “L” level. This allows
The parallel image data of DP8 to DP1 is taken into the data input terminal. On the other hand, when the LOAD signal becomes "H" level, the SWs 74 to 80 select the input on the lower side (O side) in the figure.

FIG. 12 shows a parallel / serial conversion unit 6 shown in FIG.
4 shows a timing chart in No. 4. From this, it can be seen that the parallel-serial conversion unit 64 constitutes an 8-bit shift register.

Next, FIG. 13 shows a detailed configuration of the serial-parallel converter 65 shown in FIG. Further, FIG. 14 shows a timing chart of the serial-parallel converter 65 of FIG.
As shown in FIG. 13, the serial-parallel converter 65 includes 16 DFs.
It is composed of F81 to 88, 90 to 97.

In FIG. 13, the serial data input terminal DS is connected to the data input terminal of the DFF 81.
The output of the DFF 81 is connected to the data input terminal of the DFF 82. Similarly, the DFF82 output is connected to the DFF83 data input terminal. In this way, eight DFs from DFF81 to DFF88 to which serial data is input
F are connected in series.

The conversion clock CK is input to the clock input terminals of the DFFs 81 to 88. Furthermore, DF
The outputs of F81 to 88 are connected to the data input terminals of DFF90 to 97. The LOAD signal is input to the clock input terminals of the DFFs 90 to 97, and the parallel data DP1 to DP1 to the outputs of the DFFs 81 to 88 as shown in FIG.
DFF is set by LOAD signal at the timing when DP8 is aligned
By latching 90 to 97, it is converted into 8-bit parallel data of the LOAD signal period.

In the conventional data transmission system, the number of communication lines can be reduced by performing the serial data transmission with the above-described structure, and the complexity of the print pattern and wiring can be avoided. It was

[0012]

However, in the above-mentioned conventional example, a conversion clock having a frequency eight times the required data cycle is required. As the number of bits expressing data increases, the effect obtained by serially transmitting the data also increases, but for example, a conversion clock having a frequency N times the data cycle is required for N-bit serial data transmission. It will be. In this way, the required conversion clock frequency becomes a high frequency, so that expensive X
'It is difficult to realize parallel-serial conversion when the number of bits of data is large due to problems such as the need for a TAL oscillator, measures against clock radiation noise, and the existence of CMOS operating limits. there were.

The present invention has been made to solve the above problems, and uses a data conversion apparatus and method capable of high-speed parallel-serial / serial-parallel conversion without using a high-frequency clock signal, and uses the same. It is an object of the present invention to provide a data transmission device, and a pulse width modulation device that enables pulse width modulation with a simple configuration by using the data conversion device and the method thereof.

[0014]

As one means for achieving the above-mentioned object, the data conversion apparatus of the present invention has the following configuration.

That is, input means for inputting data and its clock signal, duty reproducing means for generating a reproduced clock signal in which the duty of the clock signal is a predetermined ratio, and a triangular wave signal synchronized with the reproduced clock signal are generated. Triangular wave signal generating means, and reference signal generating means for generating a plurality of reference signals based on the triangular wave signal,
And a conversion means for converting the arrangement of the data based on the reproduction clock signal and the plurality of reference signals.

For example, the data is in a parallel array, and the converting means converts the parallel array into a serial array.

For example, the data is a serial array, and the conversion means converts the serial array into a parallel array.

For example, the converting means converts the parallel array into a serial array when the data is a parallel array, and converts the serial array into a parallel array when the data is a serial array. And

For example, the predetermined ratio is 50%.

For example, the reference signal generating means is characterized by generating the plurality of reference signals by comparing the triangular wave signal with a plurality of DC voltages having a correlation with the level of the triangular wave signal.

Further, as one method for achieving the above-mentioned object, the data conversion method of the present invention comprises the following steps.

That is, an input step of inputting data and its clock signal, a duty reproducing step of generating a reproduced clock signal in which the duty of the clock signal is set to a predetermined ratio, and a triangular wave signal synchronized with the reproduced clock signal are generated. A triangular wave signal generating step, and a reference signal generating step of generating a plurality of reference signals based on the triangular wave signal,
A conversion step of converting the arrangement of the data based on the reproduction clock signal and the plurality of reference signals.

For example, the data is a parallel array, and the parallel array is converted into a serial array in the converting step.

For example, the data is a serial array, and the serial array is converted into a parallel array in the converting step.

For example, in the converting step, when the data is a parallel array, the parallel array is converted into a serial array, and when the data is a serial array, the serial array is converted into a parallel array. Characterize.

As one means for achieving the above object, the data transmission apparatus of the present invention has the following configuration.

That is, input means for inputting parallel data and its clock signal, duty reproducing means for generating a reproduced clock signal in which the duty of the clock signal is a predetermined ratio, and a triangular wave signal synchronized with the reproduced clock signal are provided. Generated triangular wave signal generation means, reference signal generation means for generating a plurality of reference signals based on the triangular wave signal, and converting the parallel data into serial data based on the reproduced clock signal and the plurality of reference signals. It is characterized by comprising a conversion means and a transmission means for transmitting the serial data to another device.

As one means for achieving the above-mentioned object, the pulse width modulation device of the present invention has the following configuration.

That is, input means for inputting the serial image data and its clock signal, duty reproduction means for generating a reproduction clock signal in which the duty of the clock signal is a predetermined ratio, and a triangular wave signal synchronized with the reproduction clock signal. Generated triangular wave signal generation means, reference signal generation means for generating a plurality of reference signals based on the triangular wave signal, and based on the reproduction clock signal and the plurality of reference signals, the serial image data to parallel image data A conversion unit for converting, a D / A conversion unit for converting the parallel image data into analog image data, and a conversion output range of the D / A conversion unit are controlled so as to be in a range based on the level of the triangular wave signal. D / A conversion control means compares the triangular wave signal with the output from the D / A conversion means. And having a modulation means for performing pulse width modulation by the.

[0030]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 shows a block configuration of a data conversion device for realizing serial-parallel conversion and parallel-serial conversion in the present embodiment. 2A and 2B are timing charts showing the operation of FIG.

The operation of the data converter according to this embodiment can be switched to 8-bit parallel-serial conversion / 8-bit serial-parallel conversion by the mode signal S / P.
Specifically, when the S / P signal is at "L" level, parallel-serial conversion is performed, and when the S / P signal is at "H" level, serial-parallel conversion is performed.

First, the clock signal CKI having the same frequency as the parallel data cycle is input to the clock input terminal 1. The CKI is connected to the divide-by-2 circuit 2, and the divide-by-2 circuit 2 outputs the clock signal CK2 with a duty of 50% at a cycle twice that of CKI. CK2 is a variable delay circuit 3
And an exclusive logical wheel (EXOR) 4 are connected to their respective input terminals. The output DCK2 of the variable delay circuit 3 is connected to the other input terminal of the EXOR4. E
CK1 which is the output of XOR4 is connected to the triangular wave generating section 7 and the data converting section 19, and the charge pump (C
P) 5.

The charge pump 5 is constructed as shown in FIG. 3, for example, and charges the capacitor C1 with the charging current I when CK1 is at "L" level, and discharges the capacitor C1 when CK1 is at "H" level. To discharge. here,
Since the ratio of the charging current to the discharging current is 1, the output of the charge pump 5 is stabilized in DC when switching between charging and discharging, that is, when the duty of CK1 is 50%.

Returning to FIG. 1, the output of the charge pump 5 is passed through the low pass filter (LPF) 6 and the variable delay circuit 3
It is connected to the delay amount control terminal of. The variable delay circuit 3 operates as CK1 by the operation of the charge pump 5 described above.
When the "L" level period ratio of CK1 is large so that the duty of 50% becomes 50%, the output of CP5 rises and the delay amount is controlled to be small. Further, when the "H" level period ratio of CK1 is large, the CP5 output is controlled to be decreased to increase the delay amount.

The output of the triangular wave generator 7 is connected to the positive input terminals of the comparators 8-14. The output P1 of the comparator 8 is 1 at the negative input terminal of the comparator 8 for the triangular wave at the positive input terminal.
The DC comparison potential V1 that becomes a pulse having a duty of 2.5% "H" (hereinafter, simply referred to as duty) is connected. Further, the negative input terminal of the comparator 14 is connected to the DC comparison potential V7 which makes the output P7 of the comparator 14 a pulse of 87.5% duty with respect to the triangular wave of the positive input terminal. Thus, V1 is 12.5% and V7 is 87.
5% electric potential, V is applied to the negative input terminals of the comparators 9 to 13.
1, relative to V7, 25 as shown in FIGS. 2A and 2B.
% Potential V2, 37.5% potential V3, 50% potential V4, 6
The 2.5% potential V5 and the 75% potential V6 are connected.

Outputs P1 and P of the comparators 8 to 14 respectively
2, P3, P4, P5, P6 and P7 are data conversion units 19
It is connected to the. Further, P1 is a charge pump 15,
16 is connected to the input terminal, and P7 is connected to the input terminal of the charge pump 16.

An example of the structure of the charge pump 15 is shown in FIG. 4, and an example of the structure of the charge pump 16 is shown in FIG.

The circuit configuration of the charge pump 15 shown in FIG. 4 is the same as the configuration of the charge pump 5 shown in FIG. 3 described above, but the ratio of the charging current to the discharging current is different. In the charge pump 15, the discharge current / charge current ratio is “8”.
The DC stable point of the output of the charge pump 15 is obtained when the duty of P1 is 12.5%. Further, the configuration of the charge pump 16 shown in FIG. 5 is different from the configuration of the charge pump 5 shown in FIG. 3 described above in that a configuration for switching charging / discharging by P1 and switching of charging / discharging by P7 is added. There is. Here, in the charge pump 16 shown in FIG. 5, the discharging operation is performed during the “H” period of P1 and the “L” period of P7, and the charging operation is performed during the “L” period of P1 and the “H” period of P7. It is like this. Further, the charging / discharging current ratio (discharging current / charging current) by P1 and P7 is "4", and the DC stable point of the output of the charge pump 16 is P1.
The sum of the duty of P2 and the duty of the "L" period of P7 is 2
It can be obtained at 5%. The charge pumps 15 and 16 are connected to the charging / discharging current control terminal of the triangular wave generator 7 via LPFs 17 and 18, respectively.

Next, FIG. 6 shows an example of the configuration of the triangular wave generator 7. The triangular wave signal (TRI) output in FIG. 6 is
It is obtained by charging and discharging the capacitor Co with SW that opens and closes in synchronization with the input clock signal CK1. The charging / discharging current ratio at this time is "1", and the current value is set to Io.

The LPF17 output Ve1 in FIG. 1 is input to the error current generating section 20 in FIG. 6, and in the error current generating section 20, when P1 duty> 12.5%, I3 <I4, P1 duty < In the case of 12.5%, I3> I4, and in the case of P1 duty = 12.5%, error currents such that I3 = I4 are obtained.
Give to 4. That is, the offset level of the triangular wave signal is controlled so that the P1 duty becomes 12.5%.

On the other hand, the LPF18 output Ve2 is input to the error current generator 21 in FIG. 6, and when (P1 duty + P7 "L" period duty)> 25%, Io
= I1 = I2 is small, (P1 duty + P7 “L”
When the period duty) <25%, the peak level of the triangular wave signal is controlled so that Io is large, that is, (P1 duty + P7 “L” period duty) is 25%.

Summarizing the above operation, in the triangular wave generating section 7 in this embodiment, the duty of P1 is 12.5.
%, The duty of P7 is controlled to be 87.5%.

Next, the data conversion section 19 shown in FIG. 1 will be described. The data conversion unit 19 uses the above-mentioned comparator output P.
1 to P7, input terminals for CK1 and mode signal S / P,
Synchronous clock (SCK) output terminal for serial data output, serial data (DS) and parallel data (DP)
8 to DP1) are provided for each input / output (I / O) terminal. FIG. 7 shows a detailed configuration example of the data conversion unit 19.

The data conversion section 19 in this embodiment is
When the mode signal S / P is at "L" level, the parallel-serial conversion operation is performed, and the SWs 38 to 53 and 63 shown in FIG. On the other hand, when the mode signal S / P is at “H” level, the serial-parallel conversion operation is performed, and SW38 to
For 53 and 63, the O side is selected.

Hereinafter, the case where the mode signal S / P is at "L" level, that is, the parallel-serial conversion operation will be described. Note that FIG. 2A shows a timing chart at the time of parallel-serial conversion.

During the parallel-serial conversion of the present embodiment, CK1
And the comparator outputs P2, P4 and P6. As described above, the duty of each of the comparator outputs P1 and P7 is 1
It is controlled to 2.5% and 87.5%. P2, P4, P6
2A, the respective duties are 25%, 50%, and 75%, as shown in FIG. 2A, relative to P1 and P7. That is, the phases of the rising and falling edges of P2, P4, P6 and CK1 are shifted by To / 8 when the cycle of CK1 is To.

In FIG. 7, first, the parallel data is DF
Latch by CK1 rising edge at F30 to 37. Each DFF latch output is connected to one of the input terminals of AND gates (hereinafter simply referred to as AND) 54 to 61. Each of the ANDs 54 to 61 has four input terminals, and the signals input to each AND will be shown below. The latch output of each DFF is shown as Q30, for example. Further, the polarity-inverted signal is indicated by, for example, the inversion of P6 by / P6.

AND54: Q30, Q30, CK1, / P6 AND55: Q31, CK1, P6, / P4 AND56: Q32, CK1, P4, / P2 AND57: Q33, Q33, P2, CK1 AND58: Q34, Q34, / CK1 , P2 AND59: Q35, / CK1, / P2, P4 AND60: Q36, / CK1, / P4, P6 AND61: Q37, Q37, / P6, / CK1 DFF latch output by the input to each AND gate described above. There are some connections with the same gate that are duplicated, but this is the same 4-input AN in order to consider time delay etc.
This is because it is configured by D, and there is no logical problem even if the overlapping gate is replaced with a 3-input AND to eliminate the overlap.

The outputs of the ANDs 54 to 61 are OR gates 62.
The output of the OR 62 is obtained as the 8-bit parallel-serial conversion output DS (O). That is, as can be seen from FIG. 2A, the 8-bit serial output DS (O) is DF
The F latch outputs Q30 to Q37 are output one bit at a time. At the same time, CK1 is output as the synchronous clock signal SCK of serial data.

Next, the case where the mode signal S / P is at the "H" level, that is, when the serial-parallel conversion operation is described. Note that FIG. 2B shows a timing chart at the time of conversion from silicon to silicon.

At the time of Silipara conversion, first in FIG.
Serial data DS (I) input as described above
A clock signal synchronized with is connected to the CKI terminal. Then, in the triangular wave generator 7, by CK1,
The triangular wave signal TRI synchronized with CKI is generated under the same conditions as during the above-described parallel operation. Further, the pulse signals P1 to P7 are similarly generated by the respective comparators 8 to 14. During the serial-parallel conversion of the present embodiment, CK1 and the comparator outputs P1, P3, P5 and P7 are used.

In FIG. 7, all SWs select the ◯ side, and the input serial data DS (I) is connected to the data input terminals of the DFFs 22 to 29.
The clock input terminals of the DFFs 22 to 29 have P7, P5, P3, P1, / P1, / P3, /, respectively.
P5 and / P7 are input (note that / P7 indicates inversion of P7 as described above). And DFF22 ~
The outputs Q22 to 29 of 29 are connected to the data input terminals of the DFFs 30 to 37, and CK1 is input to the clock input terminals of the DFFs 30 to 37. DFF30-3
The serial-parallel conversion outputs DP8 to DP1 are respectively obtained as latch outputs by CK1 of 7.

As described above, according to the present embodiment, high-speed parallel-serial / serial-parallel conversion can be performed without using a high-frequency clock signal having a conversion rate or higher.

<Second Embodiment> The second embodiment of the present invention will be described below.
An embodiment will be described.

In an image processing apparatus such as a laser beam printer (LBP) or a digital copying machine for performing parallel-serial conversion and serial-parallel conversion of multi-valued image data, the pixel clock frequency is increased to 1 based on, for example, 8-bit image data.
It has been proposed to realize high-speed image processing, high definition, high gradation (halftone expression), etc. by performing pulse width modulation (PWM) in the pixel.

Further, in order to save space, such an image processing apparatus is also required to be downsized. Usually, in an LBP, a digital copying machine, and the like, a control unit of image data called a controller and a substrate of a laser drive unit called an engine are often separated from each other. When connecting the controller and the engine, complicated wiring such as a plurality of data lines and clock lines connecting the controllers imposes a limitation on downsizing of the device.

In the second embodiment, such a PW is used.
An example of applying the configuration for performing the parallel-serial / serial-parallel conversion described in the first embodiment to an image processing apparatus that performs M control will be described.

FIG. 8 shows a block configuration of a pulse width modulation device in the second embodiment. In FIG. 8, 91 is a controller and 92 is an engine. Note that FIG. 9 corresponds to FIG.
3 is a timing chart in the configuration shown in FIG.

Since the configurations of the parallel-serial converter 98 and serial-serial converter 99 in FIG. 8 are the same as those of the data conversion device described in the above-described first embodiment, description thereof will be omitted in the second embodiment.

In the controller 91, the input 8-bit parallel image data is converted into serial data by the parallel-serial converter 98 and transmitted to the engine 92 together with the clock SCK. In the engine 92, the input serial data is converted into 8-bit parallel data by the serial-parallel converter 99. Here, in the serial-parallel converter 99, not only the converted 8-bit parallel data but also DC voltages corresponding to 0% and 100% of the triangular wave signal at the time of serial-parallel conversion described in the first embodiment are V0, Further output as V8. And
The V0 and V8 are connected to a bias circuit 101, the triangular wave signal is further connected to a positive input terminal of a comparator 102, and parallel data (DP8 to DP1) is converted to a DA converter (DA).
C) Connected to 100.

In the bias circuit 101, the 0% potential V0 of the triangular wave is applied to the reference potential of the DAC 100 (data 00H).
The DAC output voltage) is connected to the DAC 100.
Then, based on V0 and V, the control signal VB is generated so that the DA conversion range in the DAC 100 becomes the peak level of the triangular wave signal, and is connected to the DAC 100.
The output voltage VDAC of the DAC 100 is determined in accordance with the above-mentioned condition, that is, 8-bit parallel data after serial-parallel conversion.
When data is 00H, V0 level, data is FF
When it is H, it is P of the triangular wave signal like V8 level.
It changes within the P level.

The VDAC output from the DAC 100 is connected to the negative input terminal of the comparator 102 whose triangular input signal is input to the positive input terminal. Then, the output of the comparator 102 becomes the PWM signal shown in FIG. 9, and it is possible to output the triangular wave signal, that is, the modulation output PWM in which the pulse width is modulated within one cycle of the pixel clock according to the VDAC level, that is, the pixel data.

The conversion range in the DAC 100 is 0
It is not limited to 100% to 100%.

As described above, according to the second embodiment,
By using the converter having the configuration described in the first embodiment, the circuit configuration for performing high-speed pulse width modulation (PWM) can be simplified. Further, with such a configuration, the output driver after the serial-parallel conversion can be omitted, so that the circuit configuration in the serial-parallel conversion section can be simplified and the power saving effect can be obtained.

The data amount handled in each of the above-described embodiments is not limited to 8 bits, and the circuit configuration is such that the DC value to be compared with the triangular wave signal is increased or decreased according to the required data amount. This enables processing with an arbitrary number of bits. <Other Embodiments> The present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but an apparatus including one device (for example, a copying machine). Machine, facsimile machine, etc.).

Another object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion board inserted into the computer or the function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that a case where the CPU or the like included in the function expansion board or the function expansion unit performs some or all of the actual processing and the processing realizes the functions of the above-described embodiments is also included.

[0072]

As described above, according to the present invention, high-speed parallel-serial / serial-parallel conversion can be performed without using a high-frequency clock signal having a conversion rate or higher, and serial data transmission can be easily performed. . .

Further, the configuration for performing the parallel-serial / serial-parallel conversion according to the present invention is applied to the pulse width modulation (PW) in the image processing apparatus.
By applying it to the processing M), it is possible to save the circuit of the high-speed pulse width modulation. Further, at this time, since the output driver after the serial-parallel conversion can be omitted, it is possible to obtain the effects of simplifying the circuit configuration for performing the serial-parallel conversion and saving power.

[0074]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data conversion device according to an embodiment of the present invention.

FIG. 2A is a timing chart of parallel-serial conversion in the configuration of the present embodiment.

FIG. 2B is a timing chart of serial-parallel conversion in the configuration of the present embodiment.

FIG. 3 is a diagram showing a detailed circuit configuration of a charge pump 5 in the present embodiment.

FIG. 4 is a diagram showing a detailed circuit configuration of a charge pump 15 in the present embodiment.

FIG. 5 is a diagram showing a detailed circuit configuration of a charge pump 16 in the present embodiment.

FIG. 6 is a diagram showing a detailed circuit configuration of a triangular wave generator in the present embodiment.

FIG. 7 is a diagram showing a detailed circuit configuration of a data conversion unit in the present embodiment.

FIG. 8 is a block diagram showing a configuration of a PWM modulation device in a second embodiment according to the present invention.

FIG. 9 is a timing chart showing an operation in the second embodiment.

FIG. 10 is a diagram for explaining conventional serial data transmission.

FIG. 11 is a diagram illustrating a circuit configuration example for performing conventional parallel-serial conversion.

FIG. 12 is a timing chart of a conventional circuit configuration for performing parallel-serial conversion.

FIG. 13 is a diagram showing a circuit configuration example for performing conventional serial-parallel conversion.

FIG. 14 is a timing chart in a conventional circuit configuration for performing serial-parallel conversion.

[Explanation of symbols]

 2 2 frequency divider circuit 3 variable delay circuit 4 EXOR gate 5, 15, 16 charge pump circuit 6, 17, 18 low pass filter 7 triangular wave generator 8-14, 102 comparator 19 data converter 20, 21 error current generator 98 Para-serial converter 99 Serial-para converter 100 DA converter 101 Bias circuit

Claims (12)

[Claims] 1. Input means for inputting data and its clock signal, duty reproduction means for generating a reproduction clock signal in which the duty of the clock signal is at a predetermined ratio, and triangular wave signals synchronized with the reproduction clock signal. A triangular wave signal generating means, a reference signal generating means for generating a plurality of reference signals based on the triangular wave signal, and a converting means for converting the data array based on the reproduction clock signal and the plurality of reference signals. A data conversion device comprising: 2. The data conversion apparatus according to claim 1, wherein the data is a parallel array, and the conversion means converts the parallel array into a serial array. 3. The data conversion apparatus according to claim 1, wherein the data is a serial array, and the conversion means converts the serial array into a parallel array. 4. The converting means converts the parallel array to a serial array when the data is a parallel array, and converts the serial array to a parallel array when the data is a serial array. The data conversion device according to claim 1. 5. The data conversion device according to claim 1, wherein the predetermined ratio is 50%. 6. The reference signal generating means generates the plurality of reference signals by comparing the triangular wave signal with a plurality of DC voltages having a correlation with the level of the triangular wave signal. 5. The data converter according to item 5. 7. An input step of inputting data and its clock signal, a duty reproducing step of generating a reproduced clock signal in which the duty of the clock signal is set to a predetermined ratio, and a triangular wave signal synchronized with the reproduced clock signal. A triangular wave signal generating step, a reference signal generating step of generating a plurality of reference signals based on the triangular wave signal, and a converting step of converting the data array based on the reproduction clock signal and the plurality of reference signals. A data conversion method comprising: 8. The data conversion method according to claim 7, wherein the data is a parallel array, and the parallel array is converted into a serial array in the converting step. 9. The data conversion method according to claim 7, wherein the data is a serial array, and the serial array is converted into a parallel array in the converting step. 10. The converting step includes converting the parallel array into a serial array when the data is a parallel array, and converting the serial array into a parallel array when the data is a serial array. The data conversion method according to claim 7, which is characterized in that. 11. Input means for inputting parallel data and its clock signal, duty reproduction means for generating a reproduction clock signal in which the duty of the clock signal is at a predetermined ratio, and a triangular wave signal synchronized with the reproduction clock signal. Generating triangular wave signal generating means, reference signal generating means for generating a plurality of reference signals based on the triangular wave signals, and converting the parallel data into serial data based on the reproduction clock signal and the plurality of reference signals. A data transmission device comprising: a conversion unit; and a transmission unit that transmits the serial data to another device. 12. An input unit for inputting serial image data and a clock signal thereof, a duty reproducing unit for generating a reproduced clock signal in which the duty of the clock signal is a predetermined ratio, and a triangular wave signal synchronized with the reproduced clock signal. Triangular wave signal generating means, a reference signal generating means for generating a plurality of reference signals based on the triangular wave signal, and the serial image data into parallel image data based on the reproduction clock signal and the plurality of reference signals. Conversion means for converting, D / A converting means for converting the parallel image data into analog image data, and control so that a conversion output range of the D / A converting means becomes a range based on the level of the triangular wave signal. D / A conversion control means compares the triangular wave signal with the output from the D / A conversion means. The pulse width modulator, characterized in that it comprises modulation means for performing pulse width modulation, the by.