JP3420279B2 - Pixel modulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel modulation device for subjecting input image data to gradation processing or parallel-serial conversion processing.

[0002]

2. Description of the Related Art As is conventionally known, LBP
When printing a high-definition (high-gradation) video image with a (laser beam printer), the PWM pixel that controls the beam irradiation time on a pixel-by-pixel basis for the laser light amount that correlates with the image density (toner adhesion amount) It is modulating.

FIG. 20 shows an example of a conventional PWM pixel modulation circuit. Further, FIG. 21 is a timing chart showing the operation of FIG. Here, to the input terminal 1, a video clock (FIG. 21 (a)) representing a pixel unit synchronized with a BD (beam detect) pulse indicating a horizontal reference position on the paper is input, and is input via the 1/2 counter 2. 21D, a triangular wave generating circuit 73 generates a triangular wave synchronized with the video clock as shown in FIG.

On the other hand, pixel data (FIG. 21B) for setting the print density of each pixel is input to the input terminal 72, for example, 8 pixels.
Input in bits. Then, in the DA converter 45, first, the input pixel data is latched by the video clock to obtain the pixel data (FIG. 21C), and then the FIG.
It is converted into an analog voltage corresponding to each pixel data shown in (d) and input to the comparator 27.

As shown in FIG. 21D, the comparator 27 outputs a laser drive pulse whose pulse width is modulated in accordance with each pixel data by the input triangular wave signal and the pixel analog voltage (FIG. 21). (E)).

Since the laser beam is emitted when the laser driving pulse shown in FIG. 21 (e) is at the H level,
When the pixel data is D _{N + 2} , it is "dark pixel", and conversely, D
_{When it is N + 1} , it corresponds to "pale pixel". Since the print density is very sensitive to the pulse width (irradiation time), not only the peak level value and the DC offset value of the triangular wave can be set, but also the above condition is stable.

FIG. 22 shows a conventional triangular wave generating circuit 73. The video clock input to the input terminal 17 has a waveform shaping amplifier 7 in order to remove noise such as ringing.
The waveform is shaped in 4, and a triangular wave is formed by a time constant circuit having a time constant T = R ₁ · C _{5 which} is appropriately larger than the clock cycle.

The level of this triangular wave can be set by the resistance value of R ₁ . Further, the DC offset can be set by the variable resistor VR ₁ via the sufficiently large capacitor C ₆ . In order to ensure the linearity of the slope of the triangular wave, it is necessary to set the time constant T to about 3 times the video clock period.

In addition, for the pixel modulation, there is also a method of arbitrarily modulating a unit obtained by dividing the pixel clock period by N according to the pixel data.

FIG. 23 shows an example in which the character "A" is represented by a digital signal. When FIG. 23 (A) is an ideal form, FIG. 23 (B) is expressed in pixel clock units. As can be seen from this (B), the resolution is low and the linearity of the diagonal line is impaired (the curve is also the same), so that it cannot be expressed as a clear image. What improved this (C)
Shown in.

FIG. 23C shows an example in which the pixel modulation is arbitrarily performed in a unit obtained by dividing the pixel clock cycle of FIG. 23B into four.

Next, the modulation operation of FIG. 23C will be described with reference to FIG.
The timing chart shown in FIG. In FIG. 24, SK1 is the same as the image clock expressing FIG. Further, SK2 is a clock signal having a frequency four times that of SK1, and A to D are modulation data for modulating 1/4 unit of the pixel clock. Modulation is 4 from D1 to D4
Bit-parallel data is converted by parallel-serial conversion at the timing of SK2.

This parallel-serial conversion can be easily performed by a shift register. FIG. 25 shows a shift register circuit, and FIG. 26 shows an example of its timing chart.

As described above, the image is improved as shown in FIG. 23C by the clock four times as large as the pixel clock shown in FIG. 23B and the 4-bit modulation data.

[0015]

However, as shown in FIG.
~ The conventional pixel modulation device described with reference to Fig. 26 has the following drawbacks.

1) Since the duty of the input clock signal is not guaranteed, it is necessary to generate at least a double frequency clock signal. Moreover, in the LBP system in which high-definition / high-speed printing is highly demanded, higher frequency is required, and an expensive crystal oscillator block is required.

2) In order to adjust the generation level of the triangular wave signal to the output characteristic of a general high speed DA converter, 0.6
It is necessary to secure about 0.7 Vpp. For this reason,
The buffer must be driven at a large level of about 12 volts, which is disadvantageous in terms of IC structure.

3) Since the time constant T for determining the triangular wave level is affected by environmental changes, when used for the pixel modulation in the LBP, the actual condition is that the temperature is controlled. This is a heavy load in constructing the PWM pixel modulation system of LBP.

4) Adjustment of the triangular wave level and offset value cannot independently determine the PWM characteristics, which makes adjustment extremely difficult.

5) Since N times as many clocks are required to divide the pixel clock period into N, the clock frequency becomes too high to cope with high speed and high definition, and 80 to 1
Above 00 MHz, high-speed ECL logic and expensive crystal oscillator are required.

Therefore, in view of the above points, an object of the present invention is to provide a pixel modulation device capable of forming a highly stable, high-speed and high-definition image without using a high-frequency clock.

[0022]

In order to achieve such an object, the present invention provides a pixel modulator for performing pixel modulation for gradation processing on individual pixels forming a visible image corresponding to image data. In a triangular wave generating means for generating a triangular wave signal synchronized with an input clock signal, a plurality of comparing means for comparing the triangular wave signal with a plurality of threshold values, and based on an output from at least one of the comparing means, And a phase control means for controlling the duty of the input clock signal. Here, the phase control means,
The input clock signal is frequency-divided, and the first variable pulse delay means capable of arbitrarily delaying the frequency-divided clock is provided, and the duty of the input clock signal is controlled based on the output from the predetermined comparison means. It is a thing. The triangular wave signal generating circuit including the triangular wave generating means, the comparing means, and the phase control means includes a first control loop for managing the level of the triangular wave signal and a second control for managing the DC offset of the triangular wave signal. It has a loop.

In addition, a control means for inputting a control value that defines the level of the triangular wave signal and a control value that defines the DC offset of the triangular wave signal may be provided, or in addition, the control value may be input. When pixel modulation is performed with N times as many pixels as the minimum unit pixel corresponding to the clock as one unit, the pixel modulation phase control means is provided which can vary the pixel modulation phase in units of 1/2 cycle of the input clock cycle. be able to.

In addition to the above configuration of the present invention,
A plurality of pulse delay means having a delay amount correlated with the delay amount of the first variable pulse delay means, an output of the first variable pulse delay means, and a parallel controlled by outputs of the plurality of pulse delay means. It is also possible to output the parallel-serial converted data under a predetermined condition by including a serial conversion means. In addition, it is also possible to adopt a configuration including an output control means for forcibly controlling the pixel modulation output to the high level and the low level.

[0025]

According to the present invention, when the triangular wave signal used for the PWM modulation is generated, the charging / discharging is switched at the time when the level of the input clock signal is changed to generate the triangular wave signal synchronized with the input clock signal, and a plurality of predetermined signals are generated. The levels are compared with a threshold value and converted into multiple pulses, the triangular wave level and offset value are detected using these multiple pulses, and the current value of the charging (discharging) current source is controlled by the obtained error signal. At the same time, the duty of the input clock signal can be controlled to generate a predetermined triangular wave signal.

Further, by inputting a voltage having a correlation with the bias of the triangular wave signal, a voltage having a correlation with the level and offset of the triangular wave signal can be stably output, and a stable PW can be obtained.
It is possible to perform M modulation.

Further, by utilizing a means for controlling the duty of the input clock and providing a delay means having a correlation therewith, a new phase is created within the pixel clock period, and the parallel phase is obtained without using the high frequency clock.
It becomes possible to perform serial conversion.

[0028]

EXAMPLES Hereinafter, each example of the present invention will be described in detail.

First Embodiment FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 2 shows a timing chart for explaining FIG. Figure 1
In terminal 1, for example, like a video clock,
At the timing of a certain sync signal NHD, the clock signal is missing and the sync clock signal SCK whose phase jumps is input. Since the duty of the input clock signal cannot be guaranteed, it is necessary to reproduce the duty of the clock signal first.

The clock signal SCK input to the terminal 1 is input to the first triangular wave generating circuit 34, and the first triangular wave generating circuit 34 supplies the clock signal SK1 reproduced with a duty of 50% to the terminal 37, and , Duty 50%
Clock signal DLSK with a phase difference of 90 ° with SK1
1 is output to the terminal 38, and a triangular wave signal with a duty of 50% having a rising slope in the HI section of SK1 and a falling slope in the LO section is output.

SK1 further has 1/2 counter 35 and 1 /
3 output to the counter 36, each output is switched and selected by the SW25 controlled by the mode signal M5,
It is input to the second triangular wave generation circuit 26. At this time SW
25 has a polarity of M5 = 0, 1/2 counter output side, M5
= 1 selects the 1/3 counter output side.

The second triangular wave generating circuit 26 outputs a triangular wave signal having a duty of 50% and having a rising slope in the HI section of the input clock signal and a falling slope in the LO section.

Output TRI of the first triangular wave generating circuit 34
Output TRI2 of the first and second triangular wave generation circuits 26
The duty is controlled to 50%, and the triangular wave level and the DC offset are controlled to certain specified values.

TRI1 is input to the positive input terminal of the comparator 27, and TRI2 is input to the positive input terminal of the comparator 28. A first output VDA1 and a second output VDA2 of the DA converter 45 (hereinafter abbreviated as DAC) are input to the negative inputs of the comparators 27 and 28, respectively.

The LSB level of VDA1 of the DAC 45 is
L controlled by the adjusting terminal 41 of the LSB adjusting circuit 39
Is determined by the first output VL1 of the SB adjustment circuit 39,
The LSB level of VDA2 is determined by the second output VL2 of the LSB adjusting circuit 39 controlled by the LSB adjusting terminal 42. VL1 and VL2 are triangular wave signals TRI, respectively.
1 and TRI2 are correlated with the DC offset and the signal level, and the LSB level of the DAC 45 does not change in relation to the triangular wave signal even if there is an environmental change such as power supply fluctuation or temperature fluctuation. .

The MSB level of VDA1 of DAC45 is M
MS controlled by adjusting terminal 43 of SB adjusting circuit 40
The first output VM1 of the B adjustment circuit 40 determines V
The MSB level of DA2 is determined by the second output VM2 of the MSB adjusting circuit 40 controlled by the MSB adjusting terminal 44. Similar to VL1 and VL2, VM1 and VM2 are also correlated with the DC offset and the signal level of the triangular wave signals TRI1 and TRI2, respectively. It has a structure that does not change in relation to the signal.

The DAC 45 outputs to the negative input terminals of the comparators 27 and 28 a level corresponding to the input 8-bit pixel data (D1 to D8), for example.

The comparators 27 and 28 output the PWM signals PWM1 and PWM2 centered on the apex of the triangular wave signal according to the adjustment state of the DAC 45 and the value of the pixel data. PWM1 and PWM2 are each connected to the input terminal of SW31 and controlled by the mode signal M6.
PWM1 is output when = 0, and PWM2 is output when M6 = 1.

The output PWM of SW31 is input to one of the input terminals of SW32. The other input terminal of the SW 32 has a parallel-serial conversion circuit 30 (hereinafter,
The output PS of the PS conversion circuit) is input.

Pixel data is input to the PS conversion circuit 30 as parallel input data of lower 4 bits (D1 to D4), for example, and the above-mentioned SK1 and DL are used as clock signals.
SK1 is input. The SW 32 is controlled by the mode signal M9, and outputs PWM when M9 = 0 and PS when M9 = 1.

Next, the operation of the triangular wave generating circuit 34 will be described in detail. FIG. 3 shows an internal block diagram of the triangular wave generation circuit 34. FIG. 4 is a timing chart for explaining the operation of FIG.

In FIG. 3, the input clock signal SCK whose duty is broken as shown in FIG. 4A is divided by the frequency divider circuit 52 as shown in FIG. 4B. The divided clock signal is input to the variable pulse delay circuit 53, and
The delayed clock is output as shown in (c). This delayed clock signal is input to the exclusive OR gate circuit 54 together with the non-delayed clock, and the clock signal as shown in FIG. 4D is output to the exclusive OR output, for example.

If the delay time of the variable pulse delay circuit 53 is set to 1/2 of the input clock signal period, the exclusive OR gate circuit 54 outputs the duty-reproduced clock signal.

This clock signal is input to the triangular wave generator 55. Q6 = Q8, 2 · Q11 = Q7, Q9 = Q
10, 2 · R4 = R7 and R5 = R6. However, the equal sign for a transistor indicates that the emitter size is the same. In this case, the charging / discharging current values flowing through the capacitor C1 become equal, and the charging / discharging is switched by Q8 to generate a triangular wave signal.

This triangular wave signal is input to the comparator amplifiers 58 and 61 via the buffer 57. In the comparator amplifier 58, the triangular wave signal is input to the negative phase input, and the voltage V10 that defines the 10% level from the upper apex of the desired triangular wave signal is input to the positive phase input, as shown in FIG. 7A. To be done.

Assuming that the peak value and the offset value of the triangular wave signal are the specified values, the comparator amplifier 58 outputs a 10% negative pulse as shown in FIG. 7C.
On the other hand, in the comparator amplifier 61, the triangular wave signal is input to the positive phase input, and the voltage V90 that defines the 10% level from the lower vertex of the desired triangular wave signal is input to the negative phase input.

As described above, if the triangular wave signal has the specified value, 10% negative pulse and 90% as shown in FIG.
Negative pulses are output from the comparator amplifiers 58 and 61. These two pulses are input to the charge pump circuit 62 shown in the circuit example of FIG. 5 · Q29 = 9 · Q
33, Q33 = Q32 = Q36, Q31 = Q37, 9.
If R15 = 5 · R18 and R16 = R17 = R19, the current flowing through Q33 is 1.8 times the current value flowing when Q34 and Q37 are turned on.

Therefore, the two comparator amplifiers 5
Only when the sum of the L level periods of the output pulses P10 and P90 of 8 and 61 becomes 20% with respect to the triangular wave signal period,
The sum of the discharge current and the charge current for the capacitor C4 (see FIG. 27) is balanced and the output voltage of the charge pump circuit 62 is stabilized. By the way, since the triangular wave signal generated by the triangular wave generator 56 is generated only by the charging / discharging current with respect to the capacitor C1, the triangular wave slope is a straight line. Therefore, the triangular wave signal is generated under the equilibrium condition of the charge pump circuit 62. The peak value of is the desired specified value.

The output of the charge pump circuit 62 becomes a peak error signal by the peak error creating circuit 63, and controls the charging / discharging current value of the triangular wave signal generator 56. For example, when the peak value of the triangular wave signal is larger than the specified value, the output voltage of the charge pump circuit 62 rises and the peak error creating circuit 6
The output voltage of 3 is decreased to reduce the peak level value of the triangular wave signal. On the contrary, when the peak value of the triangular wave signal is small, the output voltage of the charge pump circuit 62 decreases, the voltage of the peak error signal increases, and the peak level value of the triangular wave signal increases to converge to the specified value.

On the other hand, the output of the comparator amplifier 58 is input to the charge pump circuit 59 shown in the circuit example of FIG. Q24 = Q26, 9 · Q23 = 10 · Q27,
By satisfying R12 = R13, 10 · R11 = 9 · R14, the average value of the charging current and the discharging current with respect to the capacitor C3 becomes equal only when the L level period of the pulse P10 becomes 10% of the triangular wave signal period. Then, the output voltage of the charge pump circuit 59 is balanced.

If the duty of the clock signal input to the triangular wave signal generator 56 is not taken, the charging current value and the discharging current value supplied to the capacitor C1 for generating the triangular wave signal are equal, and therefore the triangular wave signal The offset voltage cannot be stabilized, and therefore the charge pump circuit 59
Can't even balance.

The output of the charge pump circuit 59 is input to the offset error generation circuit 60, an offset error signal is generated and input to the variable pulse delay circuit 53, and the clock duty is controlled by varying the pulse delay time. The control of the clock duty defines the offset voltage of the triangular wave signal.

A circuit example of the variable pulse delay circuit 53 is shown in FIG. Q12 = Q22, Q13 = Q29, Q16 = Q1
8, Q14 = Q20, Q15 = Q21, and R8 = R10.

FIG. 6 is a time chart showing the operation of the variable pulse delay circuit 53. 6 (a) and 6 (b) are Q
15 / B and Q21 / B represent differential frequency-divided clock signals (/ B represents a base). 6 (c), (d)
Indicates the signal output to Q14 / E and Q20 / E (/
E represents the emitter). 6 (e) and (f) show Q1
The delayed clock signals output to 2 / E and Q22 / E are shown. The delay time td is proportional to C2 · Io · R8 / Id. Here, Id is a current flowing through Q17, and the delay time td can be controlled by the offset error signal.

Therefore, for example, when the duty of the input clock signal of Q8 / B is large (the H level period is compared to the L level period), the offset voltage of the triangular wave signal rises without being stable, and thus the charge pump circuit 59 is charged. The output voltage rises, the output voltage of the offset error creating circuit 60 falls, the current Id flowing through Q17 is reduced, and the delay time t
By reducing d, the duty of the clock signal input to Q8 / B is corrected. When the duty of the input clock signal of Q8 / B is small, the clock duty is similarly corrected.

The convergence value of the duty of the clock signal input to Q8 / B is regulated by the ratio of the charging current and the discharging current of the capacitor C1, but it is possible to suppress the variation within ± 1% in the IC circuit technology. Is.

The start-up circuit 55 outputs the output voltage of the triangular wave signal generator 56 during the clock missing period as V100 shown in FIG. 7A.
This is for fixing the lower vertex voltage of the triangular wave signal of. Q4 = Q11, Q5> 2 · Q2, R1> 2 · R3
Leave.

During the clock missing period, Q8 is turned on and the capacitor C1 is continuously charged. When V100 or less, a discharge current is supplied to the capacitor C1 from Q5 to C.
The charging of 1 is stopped at V100, and the next clock signal input is awaited.

FIG. 8 is a block diagram of the second triangular wave generating circuit 26 shown in FIG. Second triangular wave generation circuit 26
May basically have the same configuration as the triangular wave signal generation circuit for unit pixel modulation. However, in the control of the offset value of the triangular wave signal, since the clock duty of the input clock signal is secured (divided clock), the output of the offset error creating circuit 60 uses the voltage-current conversion circuit 64 in this embodiment. The error current is converted into an error current, which is added to the output of the triangular wave signal generator to control the charge / discharge current balance of the triangular wave signal generating capacitor and control the offset value of the triangular wave signal.

With this method, the number of control loops can be suppressed to two even in the second triangular wave signal generation circuit 26, and the phase, peak, and offset jitter amounts caused by the loop error can be minimized. be able to.

FIG. 9 shows a configuration example of the DAC 45. Figure 9
Shows only the system of the first output VDA1,
The system of the second output VDA2 has the same configuration. In FIG. 9, VL1 is the output of the LSB adjustment circuit 39 described above,
VM1 is the output of the MSB adjustment circuit 40.

The pixel data D1 to D8 are latched by the latch circuit at the rising edge of the clock signal SCK, and each latch output LDn is input to the control terminal of the current SW, and when LDn is HI, SW is turned on. The current value flowing through SW is determined by VM1, and if the current value is Io, the output VDA1 of the DAC 45 is

[0063]

## EQU1 ## When D1 to D8 = 0, VDA1 = VL1 When D1 to D8 = 1, VDA1 = VL1-R · Io Is set.

Next, the LSB adjusting circuit 39 and the MS
The B adjustment circuit 40 will be described. The LSB adjusting circuit 39 and the MSB adjusting circuit 40 are, for example, V0 to V shown in FIG.
Adjust so that the DAC 18 outputs up to 100. However, V (VLB)> V (MSB).

At this time, V0 is DC at the apex of the triangular wave signal.
V100 is the lower peak level of the triangular wave signal. As described in the explanation of the triangular wave generating circuit, the triangular wave level and its DC offset are based on the DC levels of V10 and V90.

Therefore, the output of the DAC 45 is set to V10,
Even if the signal level and the DC offset of the triangular wave signal change due to environmental changes or the like, it is possible to follow the change by making it by the function of V90 or both.

FIG. 10 shows an example of the LSB adjusting circuit 39. For example, the voltage correlated to V10 and V90 is applied to the adjustment terminal 41.

[0068]

## EQU00002 ## When Val (= n.V10 + (1-n) .V90) (0≤n≤1) is input, Q8 / C (/ C represents the collector),

[0069]

## EQU3 ## V (Q8 / C) = V10 + R2 ((1-n). (V10-V90) / R1) -I1) Therefore, by setting (I1.R2) to the same function as V10 and V90, V (Q8 / C) is the power supply voltage V
It can be adjusted regardless of CC and temperature, and can be stabilized thereafter.

For example, the LSB level adjustment range is set to V0.
~ To design for V30,

[0071]

## EQU00004 ## R2.I1 = V10-V30 = .DELTA.V20 (V10-V90) .R2 / R1 = V0-V30 = .DELTA.V30 .DELTA.V20: 20% when the triangular wave level is 100%.
The voltage at the terminal 41 (V10
˜V90), the LSB level can be adjusted to V30 when the terminal 41 voltage is V10 and V30 when the terminal 41 voltage is V90.

FIG. 11 shows an example of the MSB adjusting circuit 40. The adjustment terminal 43 has the same voltage range as the LSB adjustment terminal Val.

[0073]

[Equation 5]     Vam (= m · V10 + (l−m) · V90) (0 ≦ m ≦ 1) Is entered. Q7 / B voltage is

[0074]

[Equation 6]     V (Q7 / B) = V90 + m (V10-V90) ・ R2 / (R1 + R2) The voltage of Q10 / B is

[0075]

[Formula 7] V (Q10 / B) = V (Q7 / B) -R3 · I
By making 1 (R3 · I1) the same function as V10 and V90, V (Q10 / B) becomes a voltage having a correlation with the triangular wave bias, regardless of the power supply voltage VCC and temperature.

A portion surrounded by a broken line in FIG. 11 forms a feedback amplifier, and Q11 / B is Q10 / B.
Feedback is applied so that the potential will be the same as.
Q11 / B has output currents I2 and R8 from VL1 to Q13.
The voltage (R8 · I2) dropped due to is applied.

Here, R8 and I2 are replaced with R and I in FIG.
By setting it to o, the voltage of Q11 / B becomes M of DAC45.
It becomes SB level. Therefore, this feedback amplifier outputs a current to Q16 / C so that the MSB level of the DAC 45 becomes Q10 / B potential. The current is DAC4
It is converted into a bias of 5 and output to the DAC 45 as VM1.

For example, the adjustment range of MSB is V70 to V
To design to 100, the change width of Q7 / B is {(V
10-V90) .R2 / (R1 + R2)} to V30 (=
Designed for V70-V100).

[0079]

## EQU00008 ## R2 / (R1 + R2) = V30 / V (10/90) = 3/8 When m = 0, Q7 / B = V90, so the level shift amount by R3 is

[0080]

[Formula 9] R3 · I1 = V100−V90 = ΔV10 ΔV10: If designed to mean 10% of the triangular wave level, the voltage of the adjustment terminal 43 (V10 to V90)
Thus, the MSB level can be adjusted to V70 when the terminal 43 voltage is V10 and V100 when the terminal 43 voltage is V90.

Next, the PS conversion circuit 30 will be described. FIG. 12 shows a PS conversion circuit 3 according to an embodiment of the present invention.
0 is a block diagram, and FIG. 13 is a timing chart for explaining the operation.

In FIG. 12, SK1 is a clock signal in which the pixel clock signal SCK1 whose duty is not guaranteed is duty-reproduced by the triangular wave signal generation circuit 34 in FIG. 1, and DLSK1 is a clock having a phase difference of 90 ° with SK1. It is a signal. SCK1 is data latch 2
It is input to the clock input terminals 5 to 5. The pixel data D4 to D1 are respectively input to the data input terminals of the first to fourth D-type flip-flops (hereinafter referred to as DFF), and the respective DFFs 65 to 68 latch and output the respective data at the timing of SCK1. .

The output of the first DFF 65 to which the MSB data D4 of the pixel data is input is input to the first input terminal of the first SW 69. The output of the fourth DFF 68 to which the LSB data D1 of the pixel data is input is input to the other second input terminal of the SW 69.

A second DFF66 output, in which D3 is input to the first input terminal of SW70, and D to the second input terminal
The third DFF 67 output to which 2 is input is input. SK1 is input to the control terminals of SW69 and 70, and the output of SW69 and 70 is switched to the first input terminal white circle side when SK1 is H level and to the second input terminal black circle side when LO level. It has become.

Further, the output of SW69 is the second output of SW71.
The output of SW70 is input to the first input terminal of SW71. DLS is connected to the control terminal of SW71.
K1 is input, and the output of SW71 switches to the first input terminal white circle side when DLSK1 is HI, and to the second input terminal black circle side when LOSK.

The output of SW71 is a parallel-serial conversion output as shown in FIG. 13F.

Second Embodiment In the LBP system for performing the PWM pixel modulation, the pixel modulation is not only changed to the unit pixel or the pixel unit of 2 × 3 times as described above, but the pixel modulation phase is set to the sub-scanning unit. There is a demand to obtain a high-quality printed image by performing various pixel modulations such as controlling by.

FIG. 14 shows a second embodiment of the pixel modulation device which meets the above demand. The same numbers are assigned to blocks that operate in the same manner as in FIG.

Differences from FIG. 1 will be described here. As shown in FIG. 14, in this embodiment, SW5 is added to the first triangular wave generating circuit 46 to switch the phase of the triangular wave signal between 0 ° and 180 ° by the mode signal M1.

FIG. 15A shows a horizontal synchronizing signal NHD, FIG.
5 (b) is an input clock signal. At this time, SW5
The output clock signal of FIG. 15 (c) (M1 = "L"),
It becomes like FIG.15 (d) (M1 = "H"). However, the inversion of the clock in the shaded area in FIG. 15D results in the H level, which is not desirable for the operation of the triangular wave signal generation circuit 9, so the blanking pulse by the blanking clear circuit 6 and the gate circuit 7 Thus, the shaded period is forcibly set to the L level.

Further, when the mode M1 is at the H level, the mode M1 is input in order to reverse the output polarity of the offset error creating circuit 60 in FIG. 15 (c), (d)
The triangular wave signal shown by the dotted line indicates the output signal in each state of the triangular wave signal generation circuit 9.

On the other hand, the phase of the input clock signal of the second triangular wave generating circuit 26 can be changed by the double pixel modulation phase control circuit 47 and the triple pixel modulation phase control circuit 48.

The output of the double-pixel modulation phase control circuit 47 shows the states of modes M2 and M3 as (M3M2).
(E): (00), FIG. 15 (f): (01), FIG.
(G) :( 10), FIG. 15 (h) :( 11). In the shaded period in FIGS. 15 (g) and 15 (h), S
Since only the phase is inverted by W13, it becomes H level, which is not preferable for the operation of the triangular wave signal generation unit 26. Therefore, the blanking clear circuit 14 and the gate circuit 15 forcibly bring the shaded period to L level.

FIG. 16 shows a timing chart for explaining the operation of the triple pixel modulation phase control circuit 48. FIG.
FIG. 16A shows the horizontal synchronizing signal NHD, and FIG. 16B shows the clock signal SK1 whose duty is reproduced. SK1 is S
It is selected when the control signal M4 of W18 is LO and is input to the input terminal of the coincidence circuit 19. Exclusive OR circuit 1
The polarity of the output of 9 can be switched by the mode signal M2. When M2 is LO, SW20 outputs an exclusive OR circuit (match) output, and when M2 is HI, the polarity is inverted and output as a mismatch circuit output. .

The output of SW20 is the first and second DFF2.
It is input to the clock input terminals of 1 and 22. First,
The second DFF output has been cleared by the horizontal synchronizing signal NHD, and is forcibly set to LO during the NHD signal LO. The inverted output NQ2 of the second DFF 22 is input to the input terminal of the exclusive OR circuit 19 and the data input terminal of the first DFF, and the output Q1 of the first DFF 21 is the second DF.
It is input to the F22 data input terminal.

When the clock signal of FIG. 16B is input to the exclusive OR circuit 19, the other input terminal of the exclusive OR circuit 19 is inverted by the second DFF which has been cleared by NHD. Output NQ2 (Fig. 16 (d), initial value H
I) causes the output of the exclusive OR circuit 19 to rise from LO to HI. DFF21, DFF that uses it as a clock
22 controls the output according to the respective data (FIGS. 16 (f), (g)).

Next, when FIG. 16 (e) rises, the DFF21 and DFF22 further change as shown in FIG.
At this time, DF is generated by the rise of the exclusive OR circuit output (FIG. 16 (e)) changed by FIGS. 16 (b) and 16 (d).
The output of F22 changes, and the output of the exclusive OR circuit becomes LO. If this operation is continued, each block outputs FIG. 16 (d), (e), (f), (g) when M4 = LO and M2 = LO.

With respect to the input clock (FIG. 16B) of the triple pixel modulation phase control circuit, the DFF21 output (FIG. 16) is output.
(F) is a signal having a phase difference of 0 with a triple cycle,
The DFF22 output (FIG. 16 (g)) is a signal delayed by 120 ° in phase with respect to the DFF21 output.

In the state of M4 = LO and M2 = HI, DF
F21 inverted output is shown in FIG. 16 (h), and SW20 output is shown in FIG.
6 (i), the positive output of DFF21 is shown in FIG.
The two outputs are shown in FIG. 16 (j) has a phase delay of 60 ° in FIG. 16 (f) and 180 ° in FIG. 16 (k).

In the M4 = HI state, SW18 is gate 1
7 is selected and the clock signal (FIG. 16) masked by the blanking pulse of FIG.
(L)) is input to the input terminal of the exclusive OR circuit 19.

Since the operation after the output of the exclusive OR circuit is the same as the above-mentioned operation, the outputs of the DFF21 and DFF22 are shown in FIGS. 16 (d) to 16 (g) according to the M2 mode.
(B) The signal is delayed by one cycle. That is, in FIG.
For (f), DFF22 output is 2 when M2 = LO
When M2 = HI at 40 °, the signal is delayed by 300 ° in phase.

The outputs of DFF21 and DFF22 are SW24.
Are input to the input terminals of. The output of the exclusive OR circuit 23, which receives the mode signals M3 and M4, is connected to the control terminal of the SW24. When the output of the exclusive OR circuit 23 is LO, it is on the DFF 22 side, and when it is HI, it is DFF.
21 side is selected.

The output of the triple pixel modulation phase control circuit 48 is
When the states of the modes M2, M3, M4 are indicated by (M4M3M2), FIG. 15 (i): (000), FIG. 15 (j): (0
01), FIG. 15 (k): (010), FIG. 15 (l):
(011), FIG. 15 (m): (100), FIG.
(N): It becomes like (101).

FIG. 17 shows a single pixel modulation clock (SW5 output), a double pixel modulation clock (gate 15 output) and a triple pixel modulation clock (S) in each mode (M1 to M4).
W24 output).

Thereafter, the pixel modulation signal can be output to the output terminal 33 by the same operation as that of the first embodiment. However, the block 29 in FIG. 14 is the DAC 4 in FIG.
5, DA including LSB adjusting circuit 39 and MSB adjusting circuit
Block C is a triangular wave generator indicated by 55 to 63 excluding the duty recovery circuit in FIG.

Third Embodiment FIG. 18 shows a third embodiment of the present invention. 18, blocks that perform the same operations as in FIG. 14 are given the same numbers. Further, the output terminal 33 of FIG. 14 is connected to the forced HL control circuit 76, and the mode signals M7, M
The output state is controlled by 8.

The signal appearing at the terminal 33 is the mode signal M7.
(Forced L) Pixel data D1 to D by M8 (Forced H)
Regardless of 9, the pixel modulation signal output is forcibly HL controlled. As a result, for example, the print density is 0 or 100%.
If desired, it is possible to guarantee completely and in a wide range without using the print density set by the minimum and maximum pulse widths.

FIG. 19 shows a timing chart for explaining FIG. In FIG. 19, (a) is pixel data,
(B) is a 1 × clock triangular wave signal, and (c) is a pixel modulation output only in the PWM mode. Here, (c) outputs the minimum pulse width for the pixel data 00H indicating the print density of 0% and the maximum pulse width for the pixel data FFH indicating the print density of 100% as the pixel modulation output. this is,
This setting is necessary for effective modulation near the minimum and maximum pulse width.

However, even if the pulse width is stable in the environment, a laser driver,
Since various things such as photoconductors intervene, it is difficult to completely guarantee absolute print density of 0% and 100% due to environmental changes. Therefore, by using the forced HL mode as shown in FIG. 19D, the absolute print density is completely 0%, 100%.
Guarantee%.

Effects of the Embodiments As described above, the following effects can be obtained by the pixel modulation device to which the present invention is applied.

1) By defining the level value and offset value of the triangular wave signal by a feedback loop circuit, a triangular wave signal that is stable with respect to the power supply voltage, environmental temperature, and element variation without adjustment is generated and compared with it. By correlating the output voltage with the level value and the offset value of the triangular wave signal, it is possible to obtain a PWM pixel modulation signal that is stable with respect to the power supply voltage and the environmental temperature.

2) Since the offset value of the triangular wave signal is controlled by the duty of the clock signal input to the triangular wave generating section, it is not necessary to regulate the duty of the clock signal input to the present circuit system, and therefore 2
There is no need for a double clock, which is advantageous in terms of system configuration.

3) It is possible to generate a triangular wave signal having a good slope linearity without requiring a large power supply voltage unlike the conventional triangular wave generating circuit.

4) By adding a start-up circuit having a very simple structure, start-up characteristics can be obtained even for a synchronous clock signal such as a video clock in which a missing period exists and the clock phase changes before and after the missing period. It has an excellent configuration.

5) Since the setting of the minimum pulse width and the maximum pulse width of the PWM signal can be made completely independent, it can be easily adjusted.

6) The unit of pixel modulation can be changed by a single pixel, a double pixel, a triple pixel, and a mode signal,
Furthermore, the modulation phase is 0 °, 180 ° when single pixel modulation,
0x, 90o, 180o, 270o during 2x pixel modulation,
0x, 60o, 120o, 180o during 3x pixel modulation,
Since it can be changed to 240 ° and 300 ° in half cycle units of single pixel modulation, various pixel modulations can be performed to obtain a high-quality printed image.

7) In pixel modulation for performing N-bit serial-parallel conversion at a time interval obtained by dividing the pixel clock period by N, serial-parallel by the output of the delay circuit with a controlled delay amount and the delay circuit having a correlation therewith. By performing the conversion, it is possible to configure a system that does not require N times as many clocks.

[0118]

As described above, according to the present invention, it is possible to provide a pixel modulation device capable of forming a highly stable, high-speed and high-definition image without using a high-frequency clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing a pixel modulation device according to a first embodiment.

FIG. 2 is a timing diagram illustrating a first operation.

FIG. 3 is a diagram showing a first triangular wave generation circuit.

FIG. 4 is a timing diagram illustrating a third operation.

FIG. 5 is a diagram showing a variable delay circuit in the first embodiment.

FIG. 6 is a timing diagram illustrating the operation of FIG.

FIG. 7 is a diagram showing the concept of PWM modulation in the first embodiment.

FIG. 8 is a block diagram showing a triangular wave generation circuit in the first embodiment.

FIG. 9 is a block diagram showing a DA converter in the first embodiment.

FIG. 10 is a circuit diagram showing an LSB adjusting circuit in the first embodiment.

FIG. 11 is a circuit diagram showing an MSB adjusting circuit in the first embodiment.

FIG. 12 is a circuit diagram showing a parallel-serial conversion circuit in the first embodiment.

13 is a timing diagram illustrating the operation of FIG.

FIG. 14 is a block diagram showing a pixel modulation device according to a second embodiment.

FIG. 15 is a timing diagram illustrating the operation of FIG.

FIG. 16 is a timing diagram illustrating the operation of the triple pixel modulation phase control circuit.

FIG. 17 is a diagram showing a relationship between a pixel modulation phase and a mode signal.

FIG. 18 is a block diagram showing a pixel modulation device according to a third embodiment.

FIG. 19 is a timing chart illustrating the operation of FIG.

FIG. 20 is a block diagram showing a conventional pixel modulation device.

FIG. 21 is a timing diagram illustrating the operation of FIG. 20.

FIG. 22 is a circuit diagram showing a conventional example of a triangular wave generation circuit.

FIG. 23 is a dot image diagram of an image.

FIG. 24 is a timing diagram in conventional pixel modulation.

FIG. 25 is a block diagram showing a configuration example of a shift register.

FIG. 26 is a timing diagram illustrating the operation of FIG. 25.

FIG. 27 is a diagram illustrating a circuit example of a charge pump.

FIG. 28 is a diagram illustrating a circuit example of a charge pump.

[Explanation of symbols]

1 Clock input terminal 2 divider circuit 3 Variable pulse delay circuit 6 Blanking pulse generator 8 Variable pulse delay circuit 9 Triangular wave generation circuit 14 Blanking pulse generation circuit 16 Blanking pulse generator 21 D flip-flop 22 D flip-flop 26 Triangle wave generator 30 parallel-serial conversion circuit 33 Pixel modulation signal output terminal 35 2 frequency divider 36 3 frequency divider 39 LSB adjustment circuit 40 MSB adjustment circuit 45 DA converter 53 Variable pulse delay circuit 55 Start circuit 56 triangular wave generator 59 Charge pump 60 error creation circuit 62 Charge pump 63 Error creation circuit 64 pixel data input terminal 65 D flip-flop 66 D flip-flop 67 D flip-flop 68 D flip-flop

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-5-338257 (JP, A) JP-A-4-213220 (JP, A) JP-A-3-22611 (JP, A) JP-A-6- 21790 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60 H03K 5/04-5/07 H03K 5/13 -5/145 B41J 2/44

Claims (7)

(57) [Claims] 1. A triangle wave generating means for generating a triangle wave signal in synchronization with an input clock signal in a pixel modulator for subjecting individual pixels forming a visible image corresponding to image data to pixel modulation for gradation processing. And a plurality of comparison means for comparing the triangular wave signal with a plurality of threshold values, and a phase control means for controlling the duty of the input clock signal based on the output from at least one of the comparison means. Pixel modulator characterized by. 2. The phase control means according to claim 1, further comprising a frequency dividing means for dividing an input clock signal and a first variable pulse delay means capable of arbitrarily delaying the divided clock signal. A pixel modulation device characterized in that the duty of an input clock signal is controlled based on an output from a comparison means. 3. The triangular wave signal generating circuit comprising the triangular wave generating means, the comparing means and the phase control means according to claim 1, wherein a first control loop for managing the level of the triangular wave signal and a DC offset of the triangular wave signal. A pixel modulation device comprising a second control loop for managing a minute. 4. In addition to claim 3, a control value defining a level of the triangular wave signal, and a DC value of the triangular wave signal.
A pixel modulation device comprising a control means for inputting a control value defining an offset amount. 5. The pixel modulation phase according to claim 1, further comprising: when performing pixel modulation with N times as many pixels as a minimum unit pixel corresponding to an input clock as one unit, with a half cycle of the input clock as a unit. A pixel modulation apparatus comprising a pixel modulation phase control means capable of varying 6. In addition to claim 2, a plurality of pulse delay means having a delay amount having a correlation with a delay amount of the first variable pulse delay means, and an output of the first variable pulse delay means. A pixel modulation apparatus comprising: parallel-serial conversion means controlled by outputs of the plurality of pulse delay means, and outputting the parallel-serial converted data under a predetermined condition. 7. The pixel modulation device according to claim 1, further comprising output control means for forcibly controlling the pixel modulation output to a high level and a low level.