JP3326888B2 - Pulse width modulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation circuit applied to a laser pulse generation circuit of a laser beam printer or the like for printing characters or figures by changing the pulse width of a laser pulse. .

[0002]

2. Description of the Related Art At present, a laser beam printer is increasingly important as a printing apparatus capable of printing characters and figures with high quality and at high speed. The laser beam printer writes output information corresponding to characters and figures on a photoconductor drum with laser light, and prints an image written on the photoconductor drum by an electrophotographic method. Therefore, a technique for controlling the pulse width of a laser beam in accordance with information to be printed is one of important techniques for realizing a laser beam printer.

Conventionally, various pulse width modulation circuits have been proposed as pulse width control means for such a laser beam, and the applicant has applied a so-called reset set flip-flop (hereinafter referred to as RS-FF) to output pulses. A circuit generated by using the method has been proposed (Japanese Patent Application No. 4-210819).
In a pulse width modulation circuit using this RS-FF,
Since it is configured to generate an output pulse that rises and falls at an arbitrary timing, the RS-FF
The set pulse and the reset pulse supplied to are generated by the programmable delay circuit.

[0004]

However, when the above-mentioned pulse width modulation circuit is used in a digital copying machine or a laser beam printer, in order to reproduce the gradation more faithfully, an output pulse narrower than the pulse width of the control pulse is used. Or when two consecutive output pulses are generated through a small gap, there are the following problems.

That is, when an output pulse narrower than the pulse width of the set pulse or the reset pulse input to the RS-FF circuit is to be generated, the period in which both the set pulse and the reset pulse are at the high level "H" overlaps. However, the RS-FF circuit does not operate normally. Also, if an attempt is made to continuously generate a wide output pulse, the period in which both the set pulse and the reset pulse are at the high level “H” overlaps at the junction between the current pulse cycle and the next pulse cycle, RS-FF circuit does not operate normally. For this reason, there has been a problem that image quality is deteriorated at a connection portion between two output pulses.

In order to solve these problems, the applicant assigns priority to a control set pulse and a reset pulse of an RS-FF circuit for generating an output pulse so as to be substantially symmetric with respect to the center of the pulse period. And the priority is divided and switched between the vicinity of the center of the pulse cycle and the other area, so that the output pulse started up by the set pulse falls immediately after that by the reset pulse, and also falls by the reset pulse A pulse width modulation circuit has been proposed in which an output pulse immediately after a pulse is raised by a set pulse immediately after the pulse (Japanese Patent Application No. Hei.
-360286).

According to this circuit, there is an advantage that an output pulse narrower than the control pulse can be generated, the RS-FF circuit operates normally, and deterioration of image quality can be prevented.

FIG. 13 to FIG. 21 are waveform diagrams showing output pulses in a combination of pulse modes of the pulse width modulation circuit. In the figure, CP (Center Pulse), LP
(Left Pulse) and RP (Right Pulse) are pulse modes, which represent the center, left alignment, and right alignment modes, respectively. The gradation is expressed by a combination of a dot size and a dot position. Generally, the dot size is 3
In steps of 2 to 256 (5 bits to 8 bits), the position is set to the above-described center, left justification, or right justification with respect to the pulse period.
Printing of characters, figures, and the like is performed by appropriately combining these modes in the various modes. Also, C
P (00), LP (00), and RP (00) represent the case where the 8-bit pulse width setting data PWD is all “0” and so-called 0% pulse output is performed, and CP (FF) and LP (00)
(FF) and RP (FF) represent the case where the 8-bit pulse width setting data PWD is all “1” and a so-called 100% pulse output is performed. Note that the above "00",
“FF” indicates data represented by a hexadecimal number. Hereinafter, pulse width setting data PWD and the like are similarly represented by a hexadecimal number.

However, in this circuit, the RS-FF
Depending on the priority mode of circuit reset (RESET) and set (SET), CP → LP in FIG. 14 and LP → LP in FIG.
Sometimes, in a period shown by hatching in the figure, a so-called blank pulse in which no pulse is generated despite a period in which a pulse must be generated is generated in the eight combination pulse mode. Similarly, when RP → CP in FIG. 19 and RP → RP in FIG.
In the period indicated by hatching in the figure, a so-called offset pulse (Offset Pulse) in which a pulse is generated in spite of a period in which no pulse is generated has occurred in the eight combination pulse modes.

In digital copiers (DPPCs) and laser beam printers (LBPs), the presence of the above-mentioned blank pulse and offset pulse does not cause any problem in general use, but has an adverse effect on higher-precision gradation expression. Exert. Particularly, the offset pulse generated when the 0% pulse is set, which is the non-pulse output, is a problem, and a phenomenon occurs in which a dot is printed in a portion where nothing is printed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a pulse width modulation circuit capable of suppressing generation of a blank pulse and an offset pulse and realizing more accurate gradation expression. It is in.

[0012]

In order to achieve the above object, according to the present invention, a control pulse input at regular intervals is delayed by a given time via delay means, and the control pulse is delayed.
Input to the set input terminal and the reset input terminal of the latch means as a set pulse and a reset pulse , respectively;
A pulse width modulation circuit that modulates a pulse width of an output pulse output from a latch unit based on a control pulse input to the set input terminal and the reset input terminal, and that varies a pulse output timing according to a setting mode. And above
In the setting mode, a pulse is emitted near the center of the pulse cycle.
First mode to generate and pulse to area other than near center
And a second mode for generating
Time, and the pulse
At the time of output of all pulses for performing
Suppress the input of the reset pulse to the set input end,
In the second mode, the entirety of one cycle of the control pulse
During non-pulse output that stops pulse output for a period
Is the set pulse to the set input end of the latch means.
Input of the control pulse, and the control
When all pulses are output by using the latch
Suppress the input of the above reset pulse to the reset input terminal of the stage.
And a pulse input control means for stopping .

[0013] In the present invention, above the second mode includes a left-aligned mode and right-justified mode for the vicinity of the center of the pulse period, the input control unit, the right-aligned
Mode in which the control pulse is
When the pulse output is stopped without pulse output, the latch
Suppress input of the above set pulse to the set input terminal of the means
In the left alignment mode, one cycle of the control pulse
Pulse output over the entire period of
Is the reset input to the reset input terminal of the latch means.
Suppress pulse input .

Further, the present invention has a pulse shaping means for dividing the pulse width of the control pulse into a plurality of steps and narrowing the pulse width stepwise.

[0015]

According to the present invention, according to the set mode,
The input of the control pulse to the set input terminal and the reset input terminal of the latch means is controlled. In particular, this input control
This is performed at the time of all pulse output in which pulse output is performed over the entire period of one cycle of the control pulse or at the time of non-pulse output in which pulse output is stopped over the entire period. Thereby, the pulse width of the output pulse output from the latch means is modulated based on the control pulses input to the set input terminal and the reset input terminal. The output timing of the pulse is set to a desired timing according to the setting mode.

Further, according to the present invention, the pulse width of the control pulse is gradually narrowed into a plurality of stages by the pulse shaping means, and is input to the set input terminal and the reset input terminal of the latch means. . Thus, the blank pulse and the offset pulse can be suppressed to about the minimum pulse width at which the latch means can operate.

[0017]

FIG. 1 is a block diagram showing an embodiment of a pulse width modulation circuit according to the present invention, and FIG. 2 is a timing chart showing input / output waveforms at various parts of the circuit of FIG.

In FIG. 1, 1 is a first pulse shaper, 2 is a second pulse shaper, 3 is a third pulse shaper, 4th pulse shaper, 5 is a first programmable delay circuit (hereinafter referred to as a delay circuit), 6 Is a second delay circuit, 7 is a shifter, 8 is a first register, 9 is a second register, 10 is a third register, 11 is a first decoder, 12 is a second decoder, and 13 is a mode switch. Signal generation circuit, 14 is a set CP gate, 15 is a set LP
Gate , 16 is a first RP gate for setting, 17 is a second RP gate for setting, 18 is a 4-input OR gate, 19
Is a first CP gate for reset, and 20 is a second CP gate for reset.
CP gate, 21 is the first LP gate for reset, 2
2 is a reset RP gate, 23 is a reset second L
A P gate, 24 indicates a 5-input OR gate, and 25 indicates an RS-FF circuit with a priority selection function.

The first pulse shaper 1 has an input frequency of several tens of MHz, for example, 20 MHz to 40 MHz.
Is converted into a clock pulse CLKP1 having a narrow pulse width based on the rising edge of the clock signal CLK, and is output to the first delay circuit 5, the first pulse shaper 2, and the third register 10. Here, when passing through the first and second delay circuits 5 and 6, the pulse width is converted into a pulse width that does not eliminate the pulse.

The second pulse shaper 2 shapes the pulse width of the clock pulse CLKP ₁ outputted from the _first pulse shaper ₁ further narrower, and sets the LP gate 1 for setting.
5. Output to the reset first CP gate 19 and reset RP gate 22, respectively.

The third pulse shaper 3 generates the clock pulse CL which has been delayed by the first delay circuit 5 for a predetermined time.
Set for CP gate 14 is further narrowed shape the pulse width of the KP _1, is output to the second LP gate 23 for RP gate 16 and reset the set.

The fourth pulse shaper 4 generates a clock pulse CL which has been delayed for a predetermined time by the second delay circuit 6.
Set for RP gate 17 is further narrowed shape the pulse width of the KP _5, and outputs each of the first LP gate 21 for the second CP gate 20 and reset reset.

The first delay circuit 5 has a plurality of stages of delay gates corresponding to the first half of the pulse period T and delaying the clock pulse CLKP ₁ output by the _first pulse shaper 1 by a predetermined time and outputting the same. Select gates respectively corresponding to the delay gates are connected in series,
First decoder 11 according to pulse width setting data PWD
The clock pulse CLKP ₁ from the _first pulse shaper ₁ is delayed based on the delay time decoded by the _first and second delay circuits 6 and 9 and output to the second delay circuit 6 and the second register 9. Further, the first delay circuit 5 outputs the input clock pulse CLKP
₁ is set to the mode signal S ₅ from the approximate center of each delay gate group.
And outputs the clock pulse CLKP ₁ to the third pulse shaper 3 from the delay gate of a predetermined number of stages.

The second delay circuit 6 has a plurality of delay gates corresponding to the latter half of the pulse period T and delaying the clock pulse CLKP ₅ output from the first delay circuit 5 by a predetermined time and outputting the same. , And selection gates respectively corresponding to the delay gates are connected in series, and a clock generated by the first delay circuit 5 based on the delay time decoded by the second decoder 12 according to the pulse width setting data PWD. pulse CLKP ₅ delays, almost outputs the mode switching signal generating circuit 13 as the mode signal S ₆ from the central position, the output from the predetermined number-th delay gates a clock pulse CLKP ₅ to the fourth Parususheipa 4 of each delay gate group I do.

The first and second delay circuits 5 and 6 are connected in series, and are used to input a set pulse SET and a reset pulse RST to a set input terminal S and a reset input terminal R of the RS-FF circuit 25 as a whole. It functions as a timing generation delay circuit that generates the rising and falling timings of the output pulse PWMOUT.

The shifter 7 outputs the pulse width setting data PWD0
7 and the mode setting data PWM0,1 are input and output to the first register 8.

The first register 8 stores the input clock signal C
8-bit pulse width setting data P for setting the pulse width of the output pulse PWMOUT by the RS-FF 25 output from the shifter 7 at the rising edge of LK.
WD0 to WD7 and 2-bit mode setting data PWM
0 and 1 are fetched, and fetched data D ₈ is output to the second register 9.

The second register 9 fetches and rewrites the data D ₈ held in the first register 8 at the timing of the rising edge of the clock pulse CLKP ₅ output from the first delay circuit 5, and rewrites the first half of the clock. The data is output to the first decoder 11 and the third register 10 corresponding to the cycle.

The third register 10 is rewritten captures data D ₁₀ held by the first leading edge timing of the clock pulses CLKP ₁ output from Parususheipa 1 in the second register 9, the period second half of the clock To the second decoder 12 corresponding to
The setting data PWM is output to the mode switching signal generation circuit 13.

The first decoder 11 has a second register 9
Decodes the data D ₉ taken into the first delay circuit 5 and sets the number of delay gate outputs to be selected before the clock pulse CLKP ₁ corresponding to the next pulse period T is input to the first delay circuit 5. and, the results as well as output to the first delay circuit 5, the control terminals of the first RP gate 16 for the control signal CTL ₁₁ set for CP gate 14, set for LP gate 15, a set according to the setting data , And a reset first CP gate 19 and a reset RP gate 2
2. Output to each control terminal of the reset second LP gate 23.

The second decoder 12 has a third register 1
Decoding the captured data D ₁₀ to 0, sets whether to select the output of what stage delay gate before the clock pulse CLKP ₅ is input to the second delay circuit 6, and the results second and outputs of the delay circuit 6, a control terminal of the second RP gate 17 for setting the control signal CTL ₁₂ in accordance with the setting data and the second CP gate reset 2
0, output to each control terminal of the reset first LP gate 21.

The mode switching signal generating circuit 13, in response to input of the first delay circuit 5 by the mode signal S _5, the mode signal S ₆ of the second delay circuit 6, and a third mode setting data via PWM register 10 High level "H"
Or mode switching signal S ₁₃ at the low level "L", and outputs the mode selection terminal M of the priority selection function RS-FF circuit 25. For example, when the mode signal S ₅ by the first delay circuit 5 is input, a mode switching signal S ₁₃ and outputs a high level "H" in order to prioritize the reset pulse, the mode signal of the second delay circuit 6 When S ₆ is input, and outputs the mode switching signal S ₁₃ in order to prioritize a set pulse at the low level "L".

The setting CP gate 14 controls the input of the clock pulse output from the third pulse shaper 3 to the 4-input OR gate 18 in accordance with the control signal CTL _{11 from} the first decoder 11 in the CP mode.

The set LP gate 15 controls the input of the clock pulse output from the second pulse shaper 2 to the 4-input OR gate 18 in response to the control signal CTL _{11 from} the first decoder 11 in the LP mode.

The first RP gate 16 for setting controls the input of the clock pulse output from the third pulse shaper 3 to the 4-input OR gate 18 in response to the control signal CTL _{11 from} the first decoder 11 in the RP mode. I do. Specifically, the pulse width setting data PWD0 to PWD0 in the RP mode
When 7 is “00 (hexadecimal)” and the so-called 0% pulse setting is performed, the first RP gate 16 stops the input of the clock pulse output from the third pulse shaper 3 to the 4-input OR gate 18. Thus, the generation of the set pulse SET is suppressed.

The second RP gate for setting 17 controls the input of the clock pulse output from the fourth pulse shaper 4 to the four-input OR gate 18 according to the control signal CTL ₁₂ by the second decoder 12 in the RP mode. I do.

The four-input OR gate 18 includes a setting CP gate 14, a setting LP gate 15, and a first R for setting.
The output pulse of the P gate 16 and the output pulse of the second RP gate 17 for setting is ORed, and the result is set as the set pulse SE.
It outputs to the set input terminal S of the RS-FF circuit 25 as T.

The first CP gate for reset 19 is
In the mode, the control signal CTL ₁₁ by the first decoder ₁₁
, The input of the clock pulse output from the second pulse shaper 2 to the 5-input OR gate 24 is controlled.
Specifically, in the CP mode, the pulse width setting data P
In order to force a reset at the beginning of the clock period T regardless of the values of WD0 to WD7, this first CP gate 19 is controlled to be open.

The reset second CP gate 20 is provided by the CP
In the mode, the control signal CTL ₁₂ by the second decoder ₁₂
, The input of the clock pulse output from the fourth pulse shaper 4 to the 5-input OR gate 24 is controlled.
Specifically, the pulse width setting data PWD in the CP mode
When 0 to 7 are "FF (hexadecimal)" and so-called 100% pulse setting, reset is not applied to the beginning of the next clock cycle T forcibly reset by the first CP gate 19. The second CP gate 20
Stops the input of the clock pulse output from the fourth pulse shaper 4 to the 5-input OR gate 24, and suppresses the generation of the reset pulse RST.

The first LP gate for reset 21 is
In the mode, the control signal CTL ₁₂ by the second decoder ₁₂
, The input of the clock pulse output from the fourth pulse shaper 4 to the 5-input OR gate 24 is controlled.
Specifically, the pulse width setting data PWD in the LP mode
When 0 to 7 are "FF" and the so-called 100% pulse setting, the first LP gate 21 stops the input of the clock pulse output from the fourth pulse shaper 4 to the 5-input OR gate 24, The generation of the reset pulse RST is suppressed.

The reset RP gate 22 controls the input of the clock pulse output from the second pulse shaper 2 to the 5-input OR gate 24 in response to the control signal CTL _{11 from} the first decoder 11 in the RP mode. Specifically, in the CP mode, the pulse width setting data PWD0
This RP gate 2 is used to forcibly reset at the beginning of the clock period T regardless of the values of .about.7.
2 is controlled to the open state.

The second LP gate for reset 23 is
In the mode, the control signal CTL ₁₁ by the first decoder ₁₁
, The input of the clock pulse output from the third pulse shaper 3 to the 5-input OR gate 24 is controlled.

The 5-input OR gate 24 is connected to the first reset gate.
, A reset second CP gate 20,
The logical OR of the output pulses of the reset first LP gate 21, the reset RP gate 22, and the reset second LP gate 23 is calculated, and the result is referred to as a reset pulse RES.
The signal is output to the reset input terminal R of the RS-FF circuit 25 as ET (hereinafter abbreviated as RST).

RS-FF circuit 25 with priority selection function
Switching the mode switching signal enter the mode switching signal S ₁₃ output from the generator 13 to the mode selection terminal M, the set pulse SET priority when the mode switching signal S ₁₃ is input at a low level "L" , when the mode switching signal S ₁₃ is input at the high level "H" is switched to the reset pulse RST priority.

Next, the operation of the above configuration will be described with reference to FIGS. First, a clock signal CLK having a constant period is input to the first pulse shaper 1 and the first register 8. In the first pulse shaper 1, the input clock signal CLK is applied to a clock pulse CLKP having a narrow pulse width based on the rising edge thereof.
_{The signal} is converted to ₁ and output to the first pulse shaper 2, the first delay circuit 5, and the third register 10. The width of the clock pulses CLKP ₁ is converted into a pulse width enough to pulse not eliminated when passing through the first and second delay circuits 5 and 6. Also, in the first register 8,
At the rising timing of the input clock signal CLK,
The 8-bit pulse width setting data PWD0-7 for setting the pulse width of the output pulse PWMOUT by the RS-FF 25 taken into the shifter 7 and the 2-bit mode setting data PWM0, 1 are taken in and written. The fetched data D ₈ is output to the second register 9.

In the second pulse shaper 2, the clock pulse CLKP ₁ output from the first pulse shaper ₁
Are further narrowed and output to the setting LP gate 15, the reset first CP gate 19, and the reset RP gate 22, respectively. In the first delay circuit 5, the first clock pulse CLKP ₁ according to the first Parususheipa 1 based on the delay time which is decoded by the decoder 11 is delayed in accordance with the pulse width setting data PWD, first as a clock pulse CLKP ₅ 2 To the delay circuit 6 and the second register 9. Also, the first
In the delay circuit 5, the input clock pulse CLKP ₁ is outputted to the mode switching signal generating circuit 13 as the mode signal S ₅ from the substantially central position of each delay gate group, subjected to a predetermined delayed action from a predetermined number-th delay gates The clock pulse CLKP ₁ is output to the third pulse shaper 3.

Clock pulse C by first delay circuit 5
In the second register 9 receiving the LKP ₅ , the data D ₈ held in the first register ₈ is taken in at the rising timing of the clock pulse CLKP ₅ to rewrite the data, and the data is rewritten in the first half cycle of the clock. Output to corresponding first decoder 11 and third register 10. In the third register 10 receiving the clock pulse CLKP ₁ output from the first pulse shaper 1, the second register 10 receives the second pulse at the rising timing of the clock pulse CLKP ₁ .
Data D ₁₀ of captured held in the register 9 rewrite the data is performed, is output to a second decoder 12 corresponding to the period second half of the clock, the mode setting data PWM is mode switching signal generating circuit 13 is output.

In the second delay circuit 6 to which the clock pulse CLKP ₅ delayed by the first delay circuit 5 is input, the second pulse is decoded by the second decoder 12 in accordance with the pulse width setting data PWD. clock pulse CLKP ₅ of the first delay circuit 5 based on the delay time is delayed, the mode signal S from the substantially central position of each delay gate group
_The clock pulse CLKP ₅ subjected to a predetermined delay action is output to the fourth pulse shaper 4 from the delay gate of the predetermined number of stages as 6.

In the third pulse shaper 3 to which the clock pulse CLKP ₁ that has been delayed by the first delay circuit 5 for a predetermined time is input, the pulse width of the clock pulse CLKP ₁ is further narrowed, and the setting CP is set. Gate 1
4. RP gate 16 for setting and second L for reset
Output to P gate 23. In the fourth pulse shaper 4 to which the clock pulse CLKP ₅ delayed by the predetermined time in the second delay circuit 6 is input, the clock pulse C
Pulse width of LKP ₅ is further narrowed shaping set for R
The signal is output to the P gate 17, the second CP gate for reset 20, and the first LP gate 21 for reset.

In the first decoder 11 to which the data held in the second register 9 has been input, the input data D ₉ is decoded, and the clock pulse CLKP ₁ corresponding to the next pulse period T is supplied to the first delay circuit 5. either selects the output of what stage of the delay gates before being input is set to, the result is output to the first delay circuit 5, also generates a control signal CTL ₁₁ in accordance with the setting data and the setting mode The control terminals of the setting CP gate 14, the setting LP gate 15, the setting first RP gate 16, the reset first CP gate 19, and the reset RP gate 2
2. Output to each control terminal of the reset second LP gate 23.

Similarly, in the second decoder 12 to which the data D ₁₀ held in the third register 10 is input, the input data D ₁₀ is decoded and the clock pulse CLKP ₅
Is set before the signal is input to the second delay circuit 6, the output of the delay gate of which stage is selected. The result is output to the second delay circuit 6, and the result is determined according to the setting data and the setting mode. second R control signal CTL ₁₂ is generated sets
Control terminal of P gate 17 and second CP for reset
The signal is output to each control terminal of the gate 20 and the reset first LP gate 21.

In the mode switching signal generating circuit 13,
Mode signal S ₅ by the first delay circuit 5, the mode signal S ₆ of the second delay circuit 6, and the third register 10
Mode switching signal S ₁₃ is set to the high level "H" or low level "L" in accordance with the input mode setting data PWM is generated by, priority selection function RS-FF
The signal is output to the mode selection terminal M of the circuit 25.

Here, for example, when the first and second decoders 11 and 12 decode the setting mode to be the RP mode, the second and third decoders 11 and 12 generate the reset pulse RST at the beginning of the clock cycle T. RP reset based by the decoder 12 of the control signal CTL ₁₂
The gate 22 is controlled to open. Thus, the clock pulse C that has been subjected to the two-step pulse shape operation by the first pulse shaper 1 and the second pulse shaper 2
LKP ₁ passes through the reset RP gate 22, is input to the 5-input OR gate 24, is input as the reset pulse RST to the reset input terminal R of the RS-FF 25, and the output of the pulse is suppressed.

Then, as shown in FIG. 3A, in the RP mode, the value of the pulse width setting data PWD is "01" to "01".
In the case of “FF”, the first RP gate 16 for setting is controlled to the open state based on the control signal CTL _{11 from} the first decoder 11 in order to obtain a pulse output corresponding to the setting data, or For the second RP gate 17
It is controlled to the open state on the basis of the decoder 12 of the control signal CTL _12. Thereby, the first pulse shaper 1
And a third first Parususheipa third or fourth clock pulse CLKP ₁ or CLKP ₅ that received the pulse shaping effect of the two stages by Parususheipa 4 is for a set of passage to 4 enter the second RP gates 16 and 17 The signal is input to the OR gate 18 and set as a set pulse SET.
Pulse PWM input to the set input terminal S of the FF 25
OUT is output.

On the other hand, in the RP mode, when the value of the pulse width setting data PWD is "00" and the 0% pulse is set, as shown in FIG.
In order to suppress the input to the set input terminal S of the RS-FF 25 of T, the first RP gate 16 for setting is controlled to the closed state based on the control signal CTL ₁₁ by the first decoder 11, or 2 of RP gate 17 is controlled into a closed state based on the control signal CTL ₁₂ by the second decoder 12.

When the first and second decoders 11 and 12 decode the setting mode to be the LP mode, for example, the first and second decoders 11 and 12 generate the set pulse SET at the beginning of the clock cycle T. Decoder 11
Set for LP gate 15 is controlled to the open state based on the control signal CTL ₁₁ by. As a result, the clock pulse CLKP that has been subjected to the two-step pulse shape operation by the first pulse shaper 1 and the second pulse shaper 2
₁ is input to the 4-input OR gate 18 through the setting LP gate 15, and the set pulse SET is used as the RS-F
The pulse PWMOUT is input to the set input terminal S of F25,
Is output.

Then, as shown in FIG. 3B, in the LP mode, the value of the pulse width setting data PWD is "00" to "00".
In the case of “FE”, the second LP gate for reset 23 is controlled to the open state based on the control signal CTL _{11 from} the first decoder 11 in order to obtain a pulse output corresponding to the setting data, or reset. the first LP gate 21 use is controlled to an open state based on the control signal CTL ₁₂ by the second decoder 12. As a result, the clock pulse CLKP ₁ or CLKP ₅ subjected to the two-step pulse shaping operation by the _first pulse shaper 1 and the third pulse shaper 3 or the fourth pulse shaper 4 is used to reset the first and second LP gates 21. , 23, and is input to a 5-input OR gate 24, and is input as a reset pulse RST to the reset input terminal R of the RS-FF 25, thereby suppressing the output of the pulse.

On the other hand, in the LP mode, when the value of the pulse width setting data PWD is "FF" and the 100% pulse is set, as shown in FIG. 3B, the reset of the RS-FF 25 of the reset pulse RST is performed. to suppress the input to the input terminal R, the second LP gate 23 for resetting is controlled to the closed state based on the control signal CTL ₁₁ of the first decoder 11 or the first LP gate 2 reset,
1 is controlled into a closed state based on the control signal CTL ₁₂ by the second decoder 12.

When the first and second decoders 11 and 12 decode the setting mode to be the CP mode, a reset pulse RST is generated at the beginning of the clock cycle T, so that the second and third decoders 11 and 12 generate the reset pulse RST. Decoder 1
A first CP gate 19 for resetting is controlled to the open state 2 on the basis of the control signal CTL ₁₂ by. As a result, the clock pulse CLKP ₁ that has been subjected to the two-step pulse shape action by the _first pulse shaper 1 and the second pulse shaper 2 passes through the reset first CP gate 19 and is input to the 5-input OR gate 24, and the reset is performed. The pulse RST is input to the reset input terminal R of the RS-FF 25, and the output of the pulse is suppressed.

Then, as shown in FIG. 3C, in the CP mode, the value of the pulse width setting data PWD is changed from "00" to "00".
In the case of “FE”, first, the setting CP gate 14 is controlled to the open state based on the control signal CTL _{11 from} the first decoder 11 in order to obtain a pulse output corresponding to the setting data. As a result, the clock pulse CLKP ₁ that has been subjected to the two-step pulse shape operation by the _first pulse shaper 1 and the third pulse shaper 3 passes through the setting CP gate 14 and is input to the four-input OR gate 18, and is set as the set pulse SET. The signal is input to the set input terminal S of the RS-FF 25, and the pulse PWMOUT is output. Then, in order to suppress the pulse output, the second CP gate 20 for resetting it is controlled to the open state based on the control signal CTL ₁₂ by the second decoder 12. Thus, the first Parususheipa 1 and the fourth clock pulse CLKP ₅ that received the pulse shaping effect of the two stages by Parususheipa 4 of the second reset of CP gates 2
The signal passes through 0, is input to the 5-input OR gate 24, is input as the reset pulse RST to the reset input terminal R of the RS-FF 25, and the output of the pulse is suppressed.

On the other hand, in the CP mode, when the value of the pulse width setting data PWD is “FF” and the pulse is set to 100%, as shown in FIG. second CP gate reset based on the control signal CTL ₁₂ of the second decoder 12 is controlled to the closed state, RS-F of the reset pulse RST
The input to the reset input terminal R of the F circuit 25 is suppressed.

As described above, according to this embodiment,
In the RP mode, when the 0% pulse is set, the input of the set pulse SET to the set input terminal S of the RS-FF circuit 25 is suppressed. In the LP mode, when the 100% pulse is set,
The input of the reset pulse RST to the reset input terminal R of the RS-FF circuit 25 is suppressed. In the CP mode, the reset pulse RST is forcibly input to the reset input terminal R of the RS-FF circuit 25 at the beginning of the clock cycle T. , 100%
At the time of pulse setting, the input of the reset pulse RST to the reset input terminal R of the RS-FF circuit 25 is suppressed in the latter half, so that the generation of a blank pulse and an offset pulse at the time of setting the 100% and 0% pulses is prevented. And higher-precision gradation expression can be realized.

Further, it is possible to reduce the generation of the blank pulse and the offset pulse which have conventionally been generated depending on the combination of the pulse modes and the pulse width set value.

FIGS. 4 to 12 are waveform diagrams showing output pulses in various combinations of the CP mode, the LP mode and the RP mode when a measure is taken using the circuit of FIG. Specifically, FIG. 4 shows CP → CP, and FIG. 5 shows CP → CP.
LP, FIG. 6 is CP → RP, FIG. 7 is LP → CP, FIG. 8 is L
P → LP, FIG. 9 shows LP → RP, FIG. 10 shows RP → CP, FIG. 11 shows output pulses in the case of RP → LP, and FIG. 12 shows output pulses in the case of RP → RP.

As can be seen by comparing these figures with FIGS. 13 to 21 which are output pulse waveform diagrams of the conventional circuit, the number of combinations of modes in which a blank pulse and an offset pulse are generated is reduced from 18 to 7. . In particular, generation of large blank pulses and offset pulses as shown in FIGS. 14, 17, 19, and 21 could be prevented.

According to the present embodiment, the input clock C
First, LK is reduced as a first step so that the pulse width is reduced to such an extent that the pulse does not disappear when passing through the first and second delay circuits 5 and 6 by the first pulse shaper 1. 4, the set pulse SET and the reset pulse RST are input to the set input terminal S and the reset input terminal of the RS-FF circuit 25, respectively. RS-F offset pulse
The pulse width can be suppressed to about the minimum pulse width at which the F circuit 25 can operate. As described above, by setting the pulse shaper to two stages, the blank pulse and the offset pulse can be expressed by Formula 1
00ps. For example, 20MH
Assuming a PWM of z, 8-bit resolution, several hundreds
The blank pulse and offset pulse of ps are 1 to
It is about 2 LSB, and has almost no effect on the resolution of the final product such as a laser beam printer or digital copier.

In this embodiment, the 0% and 100% pulses are generated by adjusting the timing of the set input and the reset input in accordance with the priority mode of the RS-FF circuit 25. It goes without saying that the set input and the reset input may be restricted and generated.

[0068]

As described above, according to the present invention,
Blank pulse at so-called 100% and 0% setting,
Generation of an offset pulse can be prevented. In addition, the generation of blank pulses and offset pulses generated by the combination of pulse modes and the pulse width setting value can be reduced. Therefore, there is an advantage that higher-precision gradation expression becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a pulse width modulation circuit according to the present invention.

FIG. 2 is a timing chart showing input / output waveforms at various parts of the circuit of FIG.

FIG. 3 is a diagram for explaining an operation according to a mode of the circuit in FIG. 1;

4 shows output pulses in various combinations of CP mode, LP mode and RP mode when a measure is taken using the circuit of FIG. 1, and is a pulse waveform diagram in the case of CP → CP.

5 shows output pulses in various combinations of the CP mode, the LP mode, and the RP mode when a measure is performed using the circuit of FIG. 1, and is a pulse waveform chart in the case of CP → LP.

6 shows output pulses in various combinations of the CP mode, the LP mode, and the RP mode when a measure is performed using the circuit of FIG. 1, and is a pulse waveform chart in the case of CP → RP.

7 shows output pulses in various combinations of the CP mode, the LP mode, and the RP mode when a measure is performed using the circuit of FIG. 1, and is a pulse waveform chart in the case of LP → CP.

8 shows output pulses in various combinations of the CP mode, the LP mode, and the RP mode when a measure is performed using the circuit of FIG. 1, and is a pulse waveform chart in the case of LP → LP.

9 shows output pulses in various combinations of the CP mode, the LP mode, and the RP mode when a measure is performed using the circuit of FIG. 1, and is a pulse waveform diagram in the case of LP → RP.

FIG. 10 shows a CP when a measure is taken using the circuit of FIG. 1;
FIG. 9 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of RP → CP.

FIG. 11 is a diagram showing a CP when a measure is taken using the circuit of FIG. 1;
FIG. 7 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of RP → LP.

FIG. 12 shows a CP when a measure is taken using the circuit of FIG. 1;
FIG. 9 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of RP → RP.

FIG. 13 shows a CP when a measure is taken using a conventional circuit.
FIG. 8 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of CP → CP.

FIG. 14 shows a CP when a measure is taken using a conventional circuit.
FIG. 8 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of CP → LP.

FIG. 15 shows a CP when a measure is taken using a conventional circuit.
FIG. 9 is a pulse waveform chart showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of CP → RP.

FIG. 16 shows a CP when a measure is taken using a conventional circuit.
FIG. 9 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of LP → CP.

FIG. 17 shows a CP when a measure is taken using a conventional circuit.
FIG. 8 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of LP → LP.

FIG. 18 shows a CP when a measure is taken using a conventional circuit.
FIG. 8 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of LP → RP.

FIG. 19 is a diagram showing a CP when a measure is taken using a conventional circuit.
FIG. 9 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of RP → CP.

FIG. 20 shows a CP when a measure is taken using a conventional circuit.
FIG. 7 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of RP → LP.

FIG. 21 is a diagram showing a CP when a measure is taken using a conventional circuit.
FIG. 9 is a pulse waveform diagram showing output pulses in various combinations of the mode, the LP mode, and the RP mode, in the case of RP → RP.

[Description of Signs] 1 ... first pulse shaper 2 ... second pulse shaper 3 ... third pulse shaper 4 ... fourth pulse shaper 5 ... first programmable delay circuit 6 ... second programmable delay circuit 7 ... shifter 8 ... 1st register 9 2nd register 10 3rd register 11 1st decoder 12 2nd decoder 13 ... mode switching signal generation circuit 14 ... CP gate for setting 15 ... LP gate for setting 16 ... set First RP gate for setting 17 Second RP gate for setting 18 Four-input OR gate 19 First CP gate for reset 20 Second CP gate for reset 21 First LP gate for reset 22 Reset RP gate 23 ... second LP gate for reset 24 ... 5-input OR gate 25 ... RS-FF with priority selection function circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 5/13 H03K 7/08 B41J 3/00

Claims (3)

(57) [Claims] 1. A delayed any time via the delay means the control pulse input to the constant cycle, cell control pulse
Input to the set input terminal and the reset input terminal of the latch means as a reset pulse and a reset pulse , respectively, and modulate the pulse width of the output pulse output from the latch means based on the control pulse input to the set input terminal and the reset input terminal. to, a variable pulse width modulation circuit timing pulse output in accordance with the set mode, in the setting mode, the pulse near the center of the pulse period
The first mode to generate and the pallet
A second mode for generating a control pulse, wherein in the first mode, the entirety of one cycle of the control pulse is included.
At the time of all pulse output that outputs the pulse over the period,
Reset pulse to the reset input terminal of the latch means
Input is suppressed, and in the second mode, the control
Pulse output is stopped for the entire period of one cycle
At the time of pulse output, the latch input to the set input terminal
Suppresses the input of the set pulse and one cycle of the control pulse
Pulse output over the entire period of
Is the reset input to the reset input terminal of the latch means.
A pulse width modulation circuit comprising pulse input control means for suppressing a pulse input. 2. The second mode includes a left-justification mode and a right-justification mode with respect to the vicinity of the center of the pulse period, and the input control means is the right-justification mode,
Stop pulse output for the entire period of one pulse cycle
At the time of non-pulse output, to the set input terminal of the latch means
Suppress the input of the set pulse of
Time, and the pulse
At the time of output of all pulses for performing
2. The pulse width modulation circuit according to claim 1 , wherein input of the reset pulse to a set input terminal is suppressed . 3. The pulse width modulation circuit according to claim 1, further comprising a pulse shaping means for dividing a pulse width of the control pulse into a plurality of steps and narrowing the pulse width stepwise.