CA2020264A1 - Digital filter - Google Patents
Digital filterInfo
- Publication number
- CA2020264A1 CA2020264A1 CA 2020264 CA2020264A CA2020264A1 CA 2020264 A1 CA2020264 A1 CA 2020264A1 CA 2020264 CA2020264 CA 2020264 CA 2020264 A CA2020264 A CA 2020264A CA 2020264 A1 CA2020264 A1 CA 2020264A1
- Authority
- CA
- Canada
- Prior art keywords
- bit
- data
- input
- digital filter
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Complex Calculations (AREA)
- Image Processing (AREA)
Abstract
Abstract of the Disclosure:
A digital filter receives an input data of N bits and generates an output data obtained by totally summing partial products each of which corresponds to a product of each bit and a predetermined coefficient.
This digital filter comprises an input register for latching the input data in the form of L divided blocks each composed of M bits, a delay-latch circuit connected to the input latch and for outputting the N-bit data with a predetermined delay time, a multiplication circuit having M memories and for multiplying a predetermined coefficient to each bit for each of the M-bit blocks outputted from the input register and the delay-latch circuit, and an addition circuit for sequentially summing data, block by block, outputted from the multiplication circuit.
A digital filter receives an input data of N bits and generates an output data obtained by totally summing partial products each of which corresponds to a product of each bit and a predetermined coefficient.
This digital filter comprises an input register for latching the input data in the form of L divided blocks each composed of M bits, a delay-latch circuit connected to the input latch and for outputting the N-bit data with a predetermined delay time, a multiplication circuit having M memories and for multiplying a predetermined coefficient to each bit for each of the M-bit blocks outputted from the input register and the delay-latch circuit, and an addition circuit for sequentially summing data, block by block, outputted from the multiplication circuit.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP169442/1989 | 1989-06-29 | ||
JP16944289A JPH0828646B2 (en) | 1989-06-29 | 1989-06-29 | Digital filter |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2020264A1 true CA2020264A1 (en) | 1990-12-30 |
CA2020264C CA2020264C (en) | 1993-11-30 |
Family
ID=15886685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA 2020264 Expired - Fee Related CA2020264C (en) | 1989-06-29 | 1990-06-29 | Digital filter |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH0828646B2 (en) |
CA (1) | CA2020264C (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06169233A (en) * | 1992-07-31 | 1994-06-14 | Matsushita Electric Ind Co Ltd | Digital signal processing method and digital filter |
JPH06216712A (en) * | 1993-01-20 | 1994-08-05 | Matsushita Electric Ind Co Ltd | Digital filter |
-
1989
- 1989-06-29 JP JP16944289A patent/JPH0828646B2/en not_active Expired - Lifetime
-
1990
- 1990-06-29 CA CA 2020264 patent/CA2020264C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CA2020264C (en) | 1993-11-30 |
JPH0828646B2 (en) | 1996-03-21 |
JPH0334615A (en) | 1991-02-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |