CA2020264A1 - Digital filter - Google Patents

Digital filter

Info

Publication number
CA2020264A1
CA2020264A1 CA 2020264 CA2020264A CA2020264A1 CA 2020264 A1 CA2020264 A1 CA 2020264A1 CA 2020264 CA2020264 CA 2020264 CA 2020264 A CA2020264 A CA 2020264A CA 2020264 A1 CA2020264 A1 CA 2020264A1
Authority
CA
Canada
Prior art keywords
bit
data
input
digital filter
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA 2020264
Other languages
French (fr)
Other versions
CA2020264C (en
Inventor
Masayuki Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CA2020264A1 publication Critical patent/CA2020264A1/en
Application granted granted Critical
Publication of CA2020264C publication Critical patent/CA2020264C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Complex Calculations (AREA)
  • Image Processing (AREA)

Abstract

Abstract of the Disclosure:
A digital filter receives an input data of N bits and generates an output data obtained by totally summing partial products each of which corresponds to a product of each bit and a predetermined coefficient.
This digital filter comprises an input register for latching the input data in the form of L divided blocks each composed of M bits, a delay-latch circuit connected to the input latch and for outputting the N-bit data with a predetermined delay time, a multiplication circuit having M memories and for multiplying a predetermined coefficient to each bit for each of the M-bit blocks outputted from the input register and the delay-latch circuit, and an addition circuit for sequentially summing data, block by block, outputted from the multiplication circuit.
CA 2020264 1989-06-29 1990-06-29 Digital filter Expired - Fee Related CA2020264C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP169442/1989 1989-06-29
JP16944289A JPH0828646B2 (en) 1989-06-29 1989-06-29 Digital filter

Publications (2)

Publication Number Publication Date
CA2020264A1 true CA2020264A1 (en) 1990-12-30
CA2020264C CA2020264C (en) 1993-11-30

Family

ID=15886685

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2020264 Expired - Fee Related CA2020264C (en) 1989-06-29 1990-06-29 Digital filter

Country Status (2)

Country Link
JP (1) JPH0828646B2 (en)
CA (1) CA2020264C (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06169233A (en) * 1992-07-31 1994-06-14 Matsushita Electric Ind Co Ltd Digital signal processing method and digital filter
JPH06216712A (en) * 1993-01-20 1994-08-05 Matsushita Electric Ind Co Ltd Digital filter

Also Published As

Publication number Publication date
CA2020264C (en) 1993-11-30
JPH0828646B2 (en) 1996-03-21
JPH0334615A (en) 1991-02-14

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