JPS6438831A - Decimal subtractor - Google Patents

Abstract

PURPOSE:To reduce the increase of hardware by providing a post complement converting circuit, which converts the subtraction result of binary-coded decimals to a decimal expressed with the absolute value, and two carry look ahead circuits where decimal correction is easily performed and generating and selecting carry information for post correction and that for omission of this correction. CONSTITUTION:A first binary-coded-decimal operand 10 is inputted to one input of a binary adding circuit 2, and a second binary-coded decimal 11 is converted to a complement 12 by a complement converting circuit 1 and is inputted to the other input of circuit 2. The operand 10 and the complement 12 are used as inputs of first and second carry look ahead circuits 3 and 4 to perform carry look ahead, and the carry input of the least significant digit of the circuit 3 is fixed to '1' and that of the circuit 4 is fixed to '0'. A selecting circuit 5 selects carry information generated by the circuit 3 if a carry-out signal 13 as carry information of the most significant digit of the circuit 3 is '1', and the circuit 5 selects carry information 15 generated by the circuit 4 if this signal 13 is '0', and selected information is supplied to the circuit 2 and is inputted to a decimal correction circuit 7 through an post complement converting circuit 6.