JPS5769450A - Decimal-quadruple generating circuit - Google Patents

Decimal-quadruple generating circuit

Info

Publication number
JPS5769450A
JPS5769450A JP55142922A JP14292280A JPS5769450A JP S5769450 A JPS5769450 A JP S5769450A JP 55142922 A JP55142922 A JP 55142922A JP 14292280 A JP14292280 A JP 14292280A JP S5769450 A JPS5769450 A JP S5769450A
Authority
JP
Japan
Prior art keywords
decimal
binary
circuit
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55142922A
Other languages
Japanese (ja)
Other versions
JPS6049328B2 (en
Inventor
Fujio Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55142922A priority Critical patent/JPS6049328B2/en
Publication of JPS5769450A publication Critical patent/JPS5769450A/en
Publication of JPS6049328B2 publication Critical patent/JPS6049328B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To perform the process of arithmetic smoothly at a high speed and to utilize the 6-adding and -subtracting circuits of a decimal a metic processor, by providing the 6-adding and -subtracting circuits, which add and substrate specific digits of a decimal number respectively, before and after a binary operating device. CONSTITUTION:When a binary number is expressed as B=b0, b1-bn, we have B=4(...4(4(4X0+b0b1)+b2 b3)+...)+bn-1b 64 bn in decimal contain. Then, an input in decimal notation. Then, an input binary-coded decimal number is shifted to the left (to high-order digits side) by two bias through a shifting circuit 4 to be inputted to one input terminal of a binary arithmetic 1, and at the same time, the same input is coded by a coding circuit 8 and, after being shifted to the left by one bit through a shifting circuit 3, is inputted to a 6-adding circuit 5 which adds (0110)2, thereby supplying its output to the other input of the binary arithmetic circuit 1. Digits, which are not carried binary addition, of the output of the binary arithmetic circuit 1 are supplied to a 6-subtracting circuit 6 which substracts (0110)2, so that a required quadruple number appears at its output.
JP55142922A 1980-10-15 1980-10-15 Decimal quadruple generation circuit Expired JPS6049328B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55142922A JPS6049328B2 (en) 1980-10-15 1980-10-15 Decimal quadruple generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55142922A JPS6049328B2 (en) 1980-10-15 1980-10-15 Decimal quadruple generation circuit

Publications (2)

Publication Number Publication Date
JPS5769450A true JPS5769450A (en) 1982-04-28
JPS6049328B2 JPS6049328B2 (en) 1985-11-01

Family

ID=15326743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55142922A Expired JPS6049328B2 (en) 1980-10-15 1980-10-15 Decimal quadruple generation circuit

Country Status (1)

Country Link
JP (1) JPS6049328B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8566385B2 (en) 2009-12-02 2013-10-22 International Business Machines Corporation Decimal floating point multiplier and design structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01224516A (en) * 1988-02-29 1989-09-07 Mitsubishi Electric Corp Fluid bearing device
CA2789920C (en) * 2010-02-26 2015-09-29 Husky Injection Molding Systems Ltd. A preform suitable for blow-molding into a final shaped container

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8566385B2 (en) 2009-12-02 2013-10-22 International Business Machines Corporation Decimal floating point multiplier and design structure

Also Published As

Publication number Publication date
JPS6049328B2 (en) 1985-11-01

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