JPS6437594A - Data updating system for display memory - Google Patents

Data updating system for display memory

Info

Publication number
JPS6437594A
JPS6437594A JP62193974A JP19397487A JPS6437594A JP S6437594 A JPS6437594 A JP S6437594A JP 62193974 A JP62193974 A JP 62193974A JP 19397487 A JP19397487 A JP 19397487A JP S6437594 A JPS6437594 A JP S6437594A
Authority
JP
Japan
Prior art keywords
display
plotting
address
rewritten
sends
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62193974A
Other languages
Japanese (ja)
Inventor
Taketoshi Yasumuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62193974A priority Critical patent/JPS6437594A/en
Publication of JPS6437594A publication Critical patent/JPS6437594A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent flickering of display in a display screen especially in the case that the speed at which data is written in a display memory is higher than the period of one-frame raster scanning by displaying rewritten display data at least once. CONSTITUTION: A latch circuit 11 holds a plotting address, that a plotting processor 6 sends to a bit map memory 9, and holds the last plotting address of a series of display data rewritten by the plotting processor 6. A comparison circuit 12 compares the address held in the latch circuit 11 with a display address for read of display data, which is sent from a CRT control circuit 7, and sends a coincidence signal in the case of coincidence. A counter 13 counts the signal sent from the comparison circuit 12, and when the counted number reaches a prescribed value, the counter sends a signal to the plotting processor 6 so that it will start the write processing of a series of next display data. Consequently, rewritten blocks are certainly displayed even if the plotting speed at which display blocks are expanded in the display memory is high. Thus, flickering of the picture is prevented.
JP62193974A 1987-08-03 1987-08-03 Data updating system for display memory Pending JPS6437594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62193974A JPS6437594A (en) 1987-08-03 1987-08-03 Data updating system for display memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62193974A JPS6437594A (en) 1987-08-03 1987-08-03 Data updating system for display memory

Publications (1)

Publication Number Publication Date
JPS6437594A true JPS6437594A (en) 1989-02-08

Family

ID=16316871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62193974A Pending JPS6437594A (en) 1987-08-03 1987-08-03 Data updating system for display memory

Country Status (1)

Country Link
JP (1) JPS6437594A (en)

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