KR900702500A - Flat panel display compensation method and circuit - Google Patents

Abstract

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Description

Flat panel display compensation method and circuit

Since this is an open matter, no full text was included.

1 is a block diagram of a data processing system including a controller according to an embodiment of the present invention, FIG. 2 is a block diagram of a controller having an address start time according to an embodiment of the present invention, and FIG. Block diagram of timing generator for CRT and flat panel displays useful in embodiments.

Claims (24)

In a data processing system having a processor, a video display device, a memory for storing information, and a video display controller for receiving information from the processor, retrieving information from the memory, and providing information to the display device. The controller comprises first circuit means for generating display identification information, a plurality of display compensation circuits each operable to generate unique information, and second circuit means for receiving information from the plurality of display compensation circuits. Wherein the second circuit means is responsive to the display identification information to provide as output the video information suitable for the device identified by the display identification information, and the controller is configured to display display information suitable for the identified device. Generating To the controller, it characterized in that in response to the information. 2. The controller of claim 1 wherein the display compensation circuitry comprises a plurality of registers. The controller of claim 1, wherein the display compensation circuitry is programmed by the processor. The controller of claim 1, wherein the display compensation information is used to repeat a line of display. The controller of claim 1, wherein the compensation information is used to insert a blank line of a display. 2. The controller of claim 1 wherein the display compensation information is used to format a text display. 2. The controller of claim 1 wherein the display compensation information is used to format a graphical display. The controller as claimed in claim 1, wherein the display compensation information is used to format a font type. A controller for a data processing system of a type having a processor, a video display device, and a memory for storing video information, the controller receiving address data and clock information from the processor, retrieving video information from the memory, And providing video information to the display device to generate a video display, wherein the controller comprises first circuit means for receiving information from the display device to generate display identification information, each unique display compensation information suitable for a unique display. A plurality of display compensation circuits programmed to generate a second circuit for receiving the display identification information and the display compensation information to generate compensation logic information suitable for the identified display; Stage, and a controller comprising the means for receiving the compensation logic and the address information to generate a video address information appropriate for the identified display. 10. The apparatus of claim 9, comprising means for receiving a flat panel timing signal and a CRT timing signal, wherein the timing signal receiving means outputs a flat panel timing signal when the display device is a flat panel display and a CRT timing when the display device is a CRT. And responsive to the display identification to provide a signal. The controller of claim 9, wherein the compensation circuit comprises a plurality of registers. 10. The controller of claim 9 wherein the compensation circuitry is programmed by the processor. 10. The controller of claim 9, wherein the compensation logic information is used to repeat a horizontal line of a display. 10. The controller of claim 9, wherein the compensation logic information is used to insert a blank horizontal line of a display. 10. The controller of claim 9 wherein the compensation logic circuit is used to format video information for text display. 10. The controller of claim 9 wherein the display compensation logic information is used to format video information for graphical display. 10. The controller of claim 9, wherein the display compensation logic is used to format video information for a font type. A processor, a video display device, a memory for storing video information, and receive address, data and clock information from the processor, retrieve information from the memory, and provide video information to the display device to generate a video display. In a data processing system having a video display controller, a method for compensating video address information for controlling a video display device determines whether the display device is a CRT display or a flat panel display. Providing no video compensation, and providing video compensation if the display device is a flat panel display. 19. The method of claim 18, wherein the step of compensating comprises vertically adjusting the center of the graphical display. 19. The method of claim 18, wherein the compensating step comprises forcing the display to indicate a selected pixel font size. 19. The method of claim 18, wherein the compensating step comprises repeating horizontal lines of the display. 29. The method of claim 28, wherein the compensating step comprises inserting a blank horizontal line of the display. 19. The method of claim 18, wherein the compensating step comprises adjusting the center of the display horizontally. 19. The display of claim 18, wherein the flat panel size is determined for a selected display size when the display device is a flat panel display, no compensation is provided when the flat panel size is the same as the selected display size, and the flat panel size is selected display. Providing video compensation when larger than the size. ※ Note: The disclosure is based on the initial application.