JPS6436032A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6436032A
JPS6436032A JP19107187A JP19107187A JPS6436032A JP S6436032 A JPS6436032 A JP S6436032A JP 19107187 A JP19107187 A JP 19107187A JP 19107187 A JP19107187 A JP 19107187A JP S6436032 A JPS6436032 A JP S6436032A
Authority
JP
Japan
Prior art keywords
film
insulating film
layer
pad
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19107187A
Other languages
Japanese (ja)
Inventor
Junichi Tsuchimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP19107187A priority Critical patent/JPS6436032A/en
Publication of JPS6436032A publication Critical patent/JPS6436032A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a semiconductor device whose resistance to radioactive rays and chemicals is excellent and where a secret can be kept easily by a method wherein a passivating film to protect a circuit-formed face of a semiconductor chip is constituted by a lower-layer insulating film and an upper-layer metal film in order to protect the insulating film from the chemicals. CONSTITUTION:An insulating film 2 as a lower layer of a passivating film is formed on a circuit-formed face of a semiconductor substrate 1 where a pattern of a circuit has been formed by ion implantation or the like. Then, a metal film 3 is formed on the insulating film 2 and this film is used as an upper layer of the passivating film. This metal film 3 is formed by, e.g., gold by a vacuum evaporation operation; after that, a photoresist 4 is coated on the whole surface by a spin-coating operation or the like; an opening 4a is made in a region to form a pad. Then, the metal film 3 at the opening 4a is polished; after that, the insulating film at the opening 4a is etched by, e.g., an RIE operation. By this setup, the pad formed in advance in the semiconductor substrate 1 is exposed; if the resist 4 is removed by using acetone or the like, a wire-bonding operation of the pad can be executed.
JP19107187A 1987-07-30 1987-07-30 Semiconductor device Pending JPS6436032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19107187A JPS6436032A (en) 1987-07-30 1987-07-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19107187A JPS6436032A (en) 1987-07-30 1987-07-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6436032A true JPS6436032A (en) 1989-02-07

Family

ID=16268386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19107187A Pending JPS6436032A (en) 1987-07-30 1987-07-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6436032A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720656B2 (en) 1998-12-21 2004-04-13 Sharp Kabushiki Kaisha Semiconductor device with analysis prevention feature

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720656B2 (en) 1998-12-21 2004-04-13 Sharp Kabushiki Kaisha Semiconductor device with analysis prevention feature

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