JPS5827346A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS5827346A
JPS5827346A JP56125086A JP12508681A JPS5827346A JP S5827346 A JPS5827346 A JP S5827346A JP 56125086 A JP56125086 A JP 56125086A JP 12508681 A JP12508681 A JP 12508681A JP S5827346 A JPS5827346 A JP S5827346A
Authority
JP
Japan
Prior art keywords
wafer
integrated circuit
film
semiconductor integrated
alpha
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56125086A
Other languages
Japanese (ja)
Inventor
Takeshi Mizusawa
水沢　武
Tadashi Matsumoto
忠 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56125086A priority Critical patent/JPS5827346A/en
Publication of JPS5827346A publication Critical patent/JPS5827346A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To shorten the steps of forming a wafer of an integrated circuit by forming a film having alpha-ray stopping capacity by simultaneous treatments at the stage of forming the wafer. CONSTITUTION:After a window opening for bonding a wire is finished in a semiconductor integrated circuit wafer 1, the existing film 4 having the capacity of stopping alpha-ray generated by the spontaneous decay of radioactive substance is bonded to the entire surface of the wafer. Then, the films of the parts necessary to perform a wire bonding and a wafer scribing are removed by a photoetching technique. Numeral 2 is a bonding pad, and 3 a scribing line. In this manner, the wafer can be simultaneously treated, thereby reducing the number of the steps are compared with the method of treating individual integrated circuit chips.

Description

【発明の詳細な説明】 本発明は、集積回路の動作に有害なアルファ線Ｔｈ１Ｊ
止するためのフィルムを有する半導体集積回路の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention aims to eliminate alpha radiation Th1J, which is harmful to the operation of integrated circuits.
The present invention relates to a method of manufacturing a semiconductor integrated circuit having a film for stopping.

６４にビットダイナミック形ＭＯＳメモリのように構成
素子が微細化されている集積回路では、パッケージ材料
中に含まれる微量のウラン、トリウム等の放射性物質の
自然崩壊で発生するアルファ線が前記集積回路のチップ
表面に侵入すると、前記集積回路が誤動作を起す可能性
がある。従来のこのような問題に対し、パッケージに集
積回路のチップを搭載後、液体の合成樹脂をチップの表
面に滴下し、その後高温で合成樹脂を硬化させてアルフ
ァ線を阻止するための膜を形成していた。以上のように
、従来の方法では集積回路チップを１個１個処理しなけ
ればならないため、工数がかかるという欠点があった。In integrated circuits whose constituent elements are miniaturized, such as bit-dynamic MOS memories, alpha rays generated by the natural decay of minute amounts of radioactive substances such as uranium and thorium contained in the package material can cause damage to the integrated circuit. If it penetrates the chip surface, the integrated circuit may malfunction. To solve this conventional problem, we have developed a method that drops liquid synthetic resin onto the surface of the chip after mounting the integrated circuit chip in a package, and then hardens the synthetic resin at high temperatures to form a film that blocks alpha rays. Was. As described above, the conventional method has the disadvantage of requiring a lot of man-hours because each integrated circuit chip must be processed one by one.

本発明は、これらの問題を解決するため、集積回路のウ
ニハエ程の段階で一括処理によりアルファ線阻止能力を
有するフィルムを形成し、工数の短縮を図った半導体集
積回路の製造方法全提供するものである。In order to solve these problems, the present invention provides a method for manufacturing a semiconductor integrated circuit that reduces the number of steps by forming a film having alpha ray blocking ability through batch processing at the stage where the integrated circuit is just a sea urchin fly. It is.

以下本発明の詳細な説明する。The present invention will be explained in detail below.

本発明の製造方法を工程順に説明する。ワイヤボンディ
ング用の窓あけ工程までは、従来の製造方法と同じであ
る。本発明の製造方法では、窓あけ終了後にアルファ線
を阻止する能力を有する既製のフィルムをウェハ表面全
体に接着する。その後、ワイヤボンディングおよびウェ
ハスクライブを実施するのに必要な部分のフィルムのみ
を、光食刻技術により除去する。ここでの光食刻技術は
、集積回路のウェハ工程で使用している方法と同等であ
る。その後の工程は、従来の製造方法と同じである。The manufacturing method of the present invention will be explained step by step. The process up to the window opening process for wire bonding is the same as the conventional manufacturing method. In the manufacturing method of the present invention, a ready-made film with the ability to block alpha radiation is adhered to the entire wafer surface after the windowing is completed. Thereafter, only the portions of the film necessary for wire bonding and wafer scribing are removed by photolithography. The optical etching technique used here is equivalent to the method used in the wafer process of integrated circuits. The subsequent steps are the same as the conventional manufacturing method.

図は、−例として本発明の製造方法によりアルファ線を
阻止する能力を有するフィルムの形成が完了した場合の
ウェハの一部を示している。１は集積回路のチップ、２
社ボ／ディングパット、３はスクライプラインである。The figure shows - by way of example - a part of a wafer after the production of a film with the ability to block alpha radiation by the manufacturing method of the invention has been completed. 1 is an integrated circuit chip, 2
The board/ding pad, number 3, is the scrying line.

４の斜線部が本発明の製造方法によシ形成したアルファ
線阻止用フィルムである。The shaded area 4 is the alpha ray blocking film formed by the manufacturing method of the present invention.

本発明に利用可能な既製のフィルムの一例としては、パ
ーマネントホトポリマコーティングフィルム等がある。An example of a ready-made film that can be used in the present invention includes a permanent photopolymer coated film.

このフィルムは本来プリント基板用保護膜として開発さ
れたものであるため、アルファ線阻止用としては、フィ
ルム材料自身に含まれるアルファ線源となる放射性物質
の低減化等の改良が必要と考えられる。放射性物質の低
減化は各種の化学処理により容易に実現可能である。前
記フィルムの接着方法は、ウェハ表面に密着後、高温で
加熱することによってなされる。Since this film was originally developed as a protective film for printed circuit boards, it is considered necessary to make improvements such as reducing the amount of radioactive substances contained in the film material itself, which act as sources of alpha rays, in order to block alpha rays. Reduction of radioactive substances can be easily achieved through various chemical treatments. The film is bonded by heating it at a high temperature after adhering it to the wafer surface.

アルファ線を阻止するためのフィルムの厚すトしては、
フィルムの材料がポリイシド樹脂の場合は３０μｍ以上
の厚さがあれば、パッケージ材料から放射されるアルフ
ァ線を阻止することが可能である。The thickness of the film to block alpha radiation is
When the material of the film is polyamide resin, alpha rays emitted from the package material can be blocked if the film has a thickness of 30 μm or more.

以上説明したように、本発明は集積回路ウエノ・、−面
全体にアルファ線阻止用フィルムを接着し、光食刻技術
によシワイヤボンディングおよびウェハスクライプに必
要な部分のフィルムを除去する製造方法であるため、ウ
ェハ毎の一括処理が可能であり、個々の集積回路チップ
を処理する方法と比較して工数の短縮が図れるという利
点がある。As explained above, the present invention is a manufacturing method in which an alpha ray blocking film is adhered to the entire surface of an integrated circuit, and the film is removed at a portion necessary for wire bonding and wafer scribing using optical etching technology. Since this is a method, batch processing of each wafer is possible, which has the advantage of reducing the number of man-hours compared to a method of processing individual integrated circuit chips.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の製造方法によりアルファ線を阻止−する能
力を有するフィルムの形成が完ｒした場合のウニ・・の
一部の−ｉ４＞ｌを示す平面図である。 １・・・集積回路チップ、　　２・・・、ボンデインク
パッド、　　３・・スクライブライン、　　４・・・ア
ルファ線阻止用フィルム。 特許出願人　　日本電信電話公社 代　　理　　人　　　白　　水　　常　　雄外１名The figure is a plan view showing -i4>l of a part of a sea urchin after the formation of a film having the ability to block alpha rays is completed by the manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1...Integrated circuit chip, 2...Bonde ink pad, 3...Scribe line, 4...Alpha ray blocking film. Patent applicant: Nippon Telegraph and Telephone Public Corporation Representative: Tsune Hakusui and one other person

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路ウェハにおいてワイヤボンディング用窓
あけ終了後、当該ウェハ表面全体に放射性物質の自然崩
壊によシ発生するアルファ線を阻止する能力を有する既
製のフィルムを接着し、光食刻技術によりワイヤボンデ
ィングおよびウェハスクライブに必要な部分のフィルム
を除去することを特徴とする半導体集積回路の製造方法
。After opening a window for wire bonding on a semiconductor integrated circuit wafer, a ready-made film that has the ability to block alpha rays generated by the natural decay of radioactive substances is adhered to the entire surface of the wafer, and wire bonding is performed using optical etching technology. and a method for manufacturing a semiconductor integrated circuit, comprising removing a portion of the film necessary for wafer scribing.
JP56125086A 1981-08-10 1981-08-10 Manufacture of semiconductor integrated circuit Pending JPS5827346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56125086A JPS5827346A (en) 1981-08-10 1981-08-10 Manufacture of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56125086A JPS5827346A (en) 1981-08-10 1981-08-10 Manufacture of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5827346A true JPS5827346A (en) 1983-02-18

Family

ID=14901480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56125086A Pending JPS5827346A (en) 1981-08-10 1981-08-10 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5827346A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0696713B1 (en) * 1987-03-02 1994-11-30
JPH08274243A (en) * 1996-03-21 1996-10-18 Hitachi Ltd Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379375A (en) * 1976-12-23 1978-07-13 Nec Corp Semiconductor device
JPS5568659A (en) * 1978-11-20 1980-05-23 Hitachi Ltd Semiconductor device and manufacturing method thereof
JPS5748251A (en) * 1980-09-04 1982-03-19 Mitsubishi Electric Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379375A (en) * 1976-12-23 1978-07-13 Nec Corp Semiconductor device
JPS5568659A (en) * 1978-11-20 1980-05-23 Hitachi Ltd Semiconductor device and manufacturing method thereof
JPS5748251A (en) * 1980-09-04 1982-03-19 Mitsubishi Electric Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0696713B1 (en) * 1987-03-02 1994-11-30
JPH08274243A (en) * 1996-03-21 1996-10-18 Hitachi Ltd Semiconductor device

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