JPS6435757U - - Google Patents
Info
- Publication number
- JPS6435757U JPS6435757U JP13061887U JP13061887U JPS6435757U JP S6435757 U JPS6435757 U JP S6435757U JP 13061887 U JP13061887 U JP 13061887U JP 13061887 U JP13061887 U JP 13061887U JP S6435757 U JPS6435757 U JP S6435757U
- Authority
- JP
- Japan
- Prior art keywords
- island
- lead frame
- mounting
- pellet
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000008188 pellet Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 229910001285 shape-memory alloy Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図ａ，ｂは本考案の一実施例を示すリード
フレームの部分平面図及びＡ―Ａ′線断面図、第
２図ａ，ｂは本考案のリードフレームを使用した
半導体装置の組立工程を説明するための工程順に
示した半導体装置の断面図である。 １……アイランド、２……吊りピン、３……リ
ード、４……マンウト剤、５……半導体ペレツト
、６，７……治具。
フレームの部分平面図及びＡ―Ａ′線断面図、第
２図ａ，ｂは本考案のリードフレームを使用した
半導体装置の組立工程を説明するための工程順に
示した半導体装置の断面図である。 １……アイランド、２……吊りピン、３……リ
ード、４……マンウト剤、５……半導体ペレツト
、６，７……治具。
Claims (1)
- 半導体ペレツト搭載用アイランドを有するリー
ドフレームにおいて、前記リードフレームの材質
が形状記憶合金からなり、前記アイランドの周辺
に配置されたリードと同一平面に保持された前記
アイランドに接続され、前記アイランドに前記半
導体ペレツトをマウントした後の熱処理により記
憶された形状に変形して前記アイランドの面を前
記リードの面に対して段差をつける吊りピンを備
えたことを特徴とするリードフレーム。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13061887U JPS6435757U (ja) | 1987-08-26 | 1987-08-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13061887U JPS6435757U (ja) | 1987-08-26 | 1987-08-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6435757U true JPS6435757U (ja) | 1989-03-03 |
Family
ID=31385950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13061887U Pending JPS6435757U (ja) | 1987-08-26 | 1987-08-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6435757U (ja) |
-
1987
- 1987-08-26 JP JP13061887U patent/JPS6435757U/ja active Pending