JPS6432657A - High heat-dissipating semiconductor element loader - Google Patents

High heat-dissipating semiconductor element loader

Info

Publication number
JPS6432657A
JPS6432657A JP62189132A JP18913287A JPS6432657A JP S6432657 A JPS6432657 A JP S6432657A JP 62189132 A JP62189132 A JP 62189132A JP 18913287 A JP18913287 A JP 18913287A JP S6432657 A JPS6432657 A JP S6432657A
Authority
JP
Japan
Prior art keywords
semiconductor element
metallic plate
high heat
loader
dissipating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62189132A
Other languages
Japanese (ja)
Inventor
Koichi Tsuyama
Masashi Isono
Toshiro Okamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP62189132A priority Critical patent/JPS6432657A/en
Publication of JPS6432657A publication Critical patent/JPS6432657A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a high heat-dissipating semiconductor element loader at low cost by connecting a semiconductor element and a metallic plate by solder for heat dissipation and efficiently transmitting heat generated from the semiconductor element over the metallic plate. CONSTITUTION:An insulating layer 2 and a conductor circuit 3 are laminated onto a metallic plate 1. The downside of a semiconductor element 6 loaded onto a hole section bored so that the metallic plate 1 is exposed to one part of the insulating layer 2 and an exposed metallic surface are joined partially by solder 5 for heat dissipation. Consequently, heat generated from the semiconductor element 6 is transmitted over the metallic plate 1 extremely efficiently. Accordingly, a high heat-dissipating semiconductor element loader is acquired at low cost.
JP62189132A 1987-07-29 1987-07-29 High heat-dissipating semiconductor element loader Pending JPS6432657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62189132A JPS6432657A (en) 1987-07-29 1987-07-29 High heat-dissipating semiconductor element loader

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62189132A JPS6432657A (en) 1987-07-29 1987-07-29 High heat-dissipating semiconductor element loader

Publications (1)

Publication Number Publication Date
JPS6432657A true JPS6432657A (en) 1989-02-02

Family

ID=16235941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62189132A Pending JPS6432657A (en) 1987-07-29 1987-07-29 High heat-dissipating semiconductor element loader

Country Status (1)

Country Link
JP (1) JPS6432657A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008517459A (en) * 2004-10-14 2008-05-22 アギア システムズ インコーポレーテッド Printed circuit board assembly with improved thermal energy dissipation
JP2010532100A (en) * 2007-06-28 2010-09-30 インテル・コーポレーション Method for forming a multilayer substrate core structure using continuous microvia laser drilling and substrate core structure formed according to the method
US8440916B2 (en) 2007-06-28 2013-05-14 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008517459A (en) * 2004-10-14 2008-05-22 アギア システムズ インコーポレーテッド Printed circuit board assembly with improved thermal energy dissipation
JP2010532100A (en) * 2007-06-28 2010-09-30 インテル・コーポレーション Method for forming a multilayer substrate core structure using continuous microvia laser drilling and substrate core structure formed according to the method
US8440916B2 (en) 2007-06-28 2013-05-14 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
US8877565B2 (en) 2007-06-28 2014-11-04 Intel Corporation Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method
US9648733B2 (en) 2007-06-28 2017-05-09 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
US10306760B2 (en) 2007-06-28 2019-05-28 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method

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