JPS6432519A - Input buffer circuit with resistor - Google Patents

Input buffer circuit with resistor

Info

Publication number
JPS6432519A
JPS6432519A JP62188498A JP18849887A JPS6432519A JP S6432519 A JPS6432519 A JP S6432519A JP 62188498 A JP62188498 A JP 62188498A JP 18849887 A JP18849887 A JP 18849887A JP S6432519 A JPS6432519 A JP S6432519A
Authority
JP
Japan
Prior art keywords
signal
turned
high level
resistor
goes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62188498A
Other languages
Japanese (ja)
Inventor
Michinaga Shigiyou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62188498A priority Critical patent/JPS6432519A/en
Publication of JPS6432519A publication Critical patent/JPS6432519A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the power consumption by applying cut-off control to a stabilized resistive element of a signal input circuit in response to a change in an input signal. CONSTITUTION:A source of a transistor(TR) 4 being a signal input circuit stabilizing resistor to a buffer 2 connects to a high level voltage VDD. Moreover, a drain and a gate of the TR 4 are connected in parallel with an inverter IR3 and a signal (a) is given from an input terminal 1. With the signal (a) at a low level, an output waveform (b) of the IR 3 goes to a high level and the TR 4 is turned off. With the signal (a) at a high level or opened, the waveform (b) goes to a low level and the TR 4 is turned on. Only when the TR 4 is turned on, a leakage current (c) flows and in case of the turn-off-state, the current does not flow, then the power consumption is reduced.
JP62188498A 1987-07-27 1987-07-27 Input buffer circuit with resistor Pending JPS6432519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62188498A JPS6432519A (en) 1987-07-27 1987-07-27 Input buffer circuit with resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62188498A JPS6432519A (en) 1987-07-27 1987-07-27 Input buffer circuit with resistor

Publications (1)

Publication Number Publication Date
JPS6432519A true JPS6432519A (en) 1989-02-02

Family

ID=16224780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62188498A Pending JPS6432519A (en) 1987-07-27 1987-07-27 Input buffer circuit with resistor

Country Status (1)

Country Link
JP (1) JPS6432519A (en)

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