JPS6431450A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPS6431450A JPS6431450A JP62189110A JP18911087A JPS6431450A JP S6431450 A JPS6431450 A JP S6431450A JP 62189110 A JP62189110 A JP 62189110A JP 18911087 A JP18911087 A JP 18911087A JP S6431450 A JPS6431450 A JP S6431450A
- Authority
- JP
- Japan
- Prior art keywords
- package
- bumps
- pellets
- pellet
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To avoid an increase in the size of a chip by mounting a plurality of IC pellets in a laminated structure, and electrically connecting the pads of the pellets to inner pads. CONSTITUTION:Printed wirings 2 are formed in a package 4, bumps 6 are attached onto a pad 7 on a pellet 3, the front and rear of the pellet 3 are so disposed reversely as to electrically connect the wirings 2 on the step of the package 4 to the bumps 6, and the pellet 3 is disposed on the step of the package 4. In order to mount a plurality of pellets 3, the pellets 3 are mounted on the package 4, the bumps 6 attached to the pad 7 of the pellet 3 are electrically connected by a paper phase soldering method to the wirings 2 on the step of the package 4. Then, the wirings 2 connected to the bumps 6 become the inner pads of the package 4. Accordingly, an increase in the size of the chip can be avoided to enhance the function of a microprocessor and the like.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62189110A JPH07120744B2 (en) | 1987-07-28 | 1987-07-28 | IC package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62189110A JPH07120744B2 (en) | 1987-07-28 | 1987-07-28 | IC package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6431450A true JPS6431450A (en) | 1989-02-01 |
JPH07120744B2 JPH07120744B2 (en) | 1995-12-20 |
Family
ID=16235540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62189110A Expired - Lifetime JPH07120744B2 (en) | 1987-07-28 | 1987-07-28 | IC package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07120744B2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5586354U (en) * | 1978-12-11 | 1980-06-14 | ||
JPS62119952A (en) * | 1985-11-19 | 1987-06-01 | Nec Corp | Integrated circuit device |
-
1987
- 1987-07-28 JP JP62189110A patent/JPH07120744B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5586354U (en) * | 1978-12-11 | 1980-06-14 | ||
JPS62119952A (en) * | 1985-11-19 | 1987-06-01 | Nec Corp | Integrated circuit device |
Also Published As
Publication number | Publication date |
---|---|
JPH07120744B2 (en) | 1995-12-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2118649A1 (en) | Interconnection Structure of Electronic Parts | |
CA2171458A1 (en) | Multi-chip module | |
JPS6428945A (en) | Circuit package assembly | |
JPS6428930A (en) | Semiconductor device | |
KR970013236A (en) | Chip Scale Package with Metal Circuit Board | |
CA2108868A1 (en) | Printed circuit board with electric elements mounted thereon | |
GB2307336B (en) | Integrated circuit package and method of fabrication | |
EP0370745A3 (en) | Low-cost high-performance semiconductor chip package | |
CA2095609A1 (en) | Leadless pad array chip carrier | |
CA2061522A1 (en) | Structure of semiconductor ic chip | |
MY120334A (en) | Bump formation method | |
JPS6431450A (en) | Ic package | |
CA2273223A1 (en) | Chip-size package using a polyimide pcb interposer | |
WO1997037374A3 (en) | Method of packaging multiple integrated circuit chips in a standard semiconductor device package | |
KR970005690B1 (en) | Ball grid array lead frame | |
JPS6450539A (en) | Connection of electronic component and transfer type microlead faceplate used therefor | |
KR970013134A (en) | Heat Dissipation Structure of Ball Grid Array (BGA) Semiconductor Package Using Solder Ball as Input / Output Terminal | |
JPS6453568A (en) | Semiconductor package | |
JPS57204154A (en) | Structure of chip carrier | |
ES295772U (en) | Flat package for integrated circuit memory chips. | |
JPS6467947A (en) | Ic package substrate | |
JPS54102971A (en) | Semiconductor device | |
JPS6477135A (en) | Semiconductor device | |
JPH0336150U (en) | ||
JPS5287363A (en) | Semiconductor packdage |