JPS6427377A - Teletext multiple broadcast receiver - Google Patents

Teletext multiple broadcast receiver

Info

Publication number
JPS6427377A
JPS6427377A JP18405787A JP18405787A JPS6427377A JP S6427377 A JPS6427377 A JP S6427377A JP 18405787 A JP18405787 A JP 18405787A JP 18405787 A JP18405787 A JP 18405787A JP S6427377 A JPS6427377 A JP S6427377A
Authority
JP
Japan
Prior art keywords
data
section
teletext
cpu
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18405787A
Other languages
Japanese (ja)
Inventor
Yasuyuki Takai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP18405787A priority Critical patent/JPS6427377A/en
Publication of JPS6427377A publication Critical patent/JPS6427377A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To display effective information as a graph or a chart or the like by providing a data fetch section fetching a data of a teletext multiple broadcast, a storage section storing the data, an arithmetic processing section applying arithmetic processing based on the data from a storage section and a data storage section storing the result of arithmetic operation. CONSTITUTION:A teletext multiple data fetched in the data fetch section 1 of a teletext multiple broadcast receiver is inputted directly to a storage section 2 not through a CPU 3 based on a direct memory access transfer (DMA transfer) enable signal S1 outputted from the CPU 3 for the DMA transfer sending the data to the sotrage section 2 directly. The result of arithmetic operation outputted from the CPU 3 is inputted properly to a display section 4 through a data line D3 and displayed and inputted to a data storage section 5 through a data line D4 and stored. Then the stored data is read by a command from the CPU 3 as required and inputted to the display section 4 through the data line D3 and displayed.
JP18405787A 1987-07-22 1987-07-22 Teletext multiple broadcast receiver Pending JPS6427377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18405787A JPS6427377A (en) 1987-07-22 1987-07-22 Teletext multiple broadcast receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18405787A JPS6427377A (en) 1987-07-22 1987-07-22 Teletext multiple broadcast receiver

Publications (1)

Publication Number Publication Date
JPS6427377A true JPS6427377A (en) 1989-01-30

Family

ID=16146618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18405787A Pending JPS6427377A (en) 1987-07-22 1987-07-22 Teletext multiple broadcast receiver

Country Status (1)

Country Link
JP (1) JPS6427377A (en)

Similar Documents

Publication Publication Date Title
MY104531A (en) Data processing system with instruction tag apparatus
SE8405455L (en) DATA DISPLAY SYSTEM
WO1988006760A3 (en) Central processor unit for digital data processing system including write buffer management mechanism
EP0315321A3 (en) Multiprocessor system with multiple memories
WO1993010518A3 (en) Video/graphics memory system
TW343318B (en) Register addressing in a data processing apparatus
CA2052559A1 (en) Vector processing device comprising a reduced amount of hardware
EP0285346A3 (en) Cache memory device
EP0322769A3 (en) Data processing apparatus suitable for high speed processing
ES8606694A1 (en) Buffer storage control system.
JPS54146549A (en) Information processor
JPS6427377A (en) Teletext multiple broadcast receiver
JPS55121574A (en) Memory controller
JPS57114962A (en) Diagram managing system
JPS53129540A (en) Display system of word processor
JPS6429933A (en) Store buffer controller for buffer storage system
JPS54137943A (en) Electronic cash register
TW345637B (en) Data processor with branch target address cache and method of operation a data processor has a BTAC storing a number of recently encountered fetch address-target address pairs.
JPS54149520A (en) Dispaly unit
JPS567162A (en) Memory sharing device for arithmetic control unit
JPS5588126A (en) Data input system to electronic unit
JPS6444689A (en) Teletext receiver
JPS647130A (en) Instruction prefetch method for memory system
GB2016757A (en) Display Terminal
JPS6426098A (en) Bomb management system and bomb