JPS6426233A - Microcomputer - Google Patents
MicrocomputerInfo
- Publication number
- JPS6426233A JPS6426233A JP18109887A JP18109887A JPS6426233A JP S6426233 A JPS6426233 A JP S6426233A JP 18109887 A JP18109887 A JP 18109887A JP 18109887 A JP18109887 A JP 18109887A JP S6426233 A JPS6426233 A JP S6426233A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- signal
- bus
- instruction execution
- whole system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Advance Control (AREA)
Abstract
PURPOSE:To improve the instruction execution speed of the whole system by generating a previous notice signal for requesting a right to use a bus separately from a bus using right request signal and inhibiting new instruction fetching operation from being started according to the previous notice signal. CONSTITUTION:A microinstruction register 7 outputs a signal PFSTOP inhibiting new instruction prefetching operation from being started while notifying that a signal BREQ is generated in a cycle before a signal BREQ informing a memory access control circuit 11 of the request for the right to use the bus accompanying a memory read line. Consequently, a break of instruction execution in the waiting state of an instruction execution part 9 is eliminated and while the supply and demand balance of an operation program by instruction prefetching and instruction decoding execution is maintained, the instruction execution speed of the whole system can be improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18109887A JPS6426233A (en) | 1987-07-22 | 1987-07-22 | Microcomputer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18109887A JPS6426233A (en) | 1987-07-22 | 1987-07-22 | Microcomputer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6426233A true JPS6426233A (en) | 1989-01-27 |
Family
ID=16094799
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18109887A Pending JPS6426233A (en) | 1987-07-22 | 1987-07-22 | Microcomputer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6426233A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05100848A (en) * | 1991-10-11 | 1993-04-23 | Matsushita Electric Ind Co Ltd | Instruction pre-fetch device |
US5402421A (en) * | 1992-10-30 | 1995-03-28 | Fujitsu Limited | Bus control device and bus control method |
-
1987
- 1987-07-22 JP JP18109887A patent/JPS6426233A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05100848A (en) * | 1991-10-11 | 1993-04-23 | Matsushita Electric Ind Co Ltd | Instruction pre-fetch device |
US5402421A (en) * | 1992-10-30 | 1995-03-28 | Fujitsu Limited | Bus control device and bus control method |
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