JPS6425623A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS6425623A
JPS6425623A JP62183867A JP18386787A JPS6425623A JP S6425623 A JPS6425623 A JP S6425623A JP 62183867 A JP62183867 A JP 62183867A JP 18386787 A JP18386787 A JP 18386787A JP S6425623 A JPS6425623 A JP S6425623A
Authority
JP
Japan
Prior art keywords
goes
input
low level
output
high level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62183867A
Other languages
Japanese (ja)
Inventor
Takashi Takagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62183867A priority Critical patent/JPS6425623A/en
Publication of JPS6425623A publication Critical patent/JPS6425623A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To facilitate the correspondence to the increase in fan-in number of input by constituting an input section by a bipolar circuit and an output section by a CMOS inverter circuit in an NAND group logic circuit by the BiCMOS process. CONSTITUTION:At least one input of inputs A-D is at a low level, a minute current flows to the input via a high resistive element 1 and the collector of a multimulti-emitter Schottky transistor 2 goes also to a low level. Thus, an N-channel MOS transistor(TR) 4 is turned off and the output X goes to a high level. When all the inputs A-D are at a high level, the collector of the multi- emitter Schottky TR 2 goes also to a high level and the N-channel MOS TR 4 is turned on and the output X goes to a low level.
JP62183867A 1987-07-22 1987-07-22 Logic circuit Pending JPS6425623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62183867A JPS6425623A (en) 1987-07-22 1987-07-22 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183867A JPS6425623A (en) 1987-07-22 1987-07-22 Logic circuit

Publications (1)

Publication Number Publication Date
JPS6425623A true JPS6425623A (en) 1989-01-27

Family

ID=16143214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62183867A Pending JPS6425623A (en) 1987-07-22 1987-07-22 Logic circuit

Country Status (1)

Country Link
JP (1) JPS6425623A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157626A (en) * 1981-03-23 1982-09-29 Fujitsu Ltd Decoder circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157626A (en) * 1981-03-23 1982-09-29 Fujitsu Ltd Decoder circuit

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