JPS6425429A - Mounting of semiconductor chip - Google Patents

Mounting of semiconductor chip

Info

Publication number
JPS6425429A
JPS6425429A JP62180997A JP18099787A JPS6425429A JP S6425429 A JPS6425429 A JP S6425429A JP 62180997 A JP62180997 A JP 62180997A JP 18099787 A JP18099787 A JP 18099787A JP S6425429 A JPS6425429 A JP S6425429A
Authority
JP
Japan
Prior art keywords
electrodes
film
pattern
chip
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62180997A
Other languages
English (en)
Inventor
Hirohide Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62180997A priority Critical patent/JPS6425429A/ja
Publication of JPS6425429A publication Critical patent/JPS6425429A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Wire Bonding (AREA)
JP62180997A 1987-07-22 1987-07-22 Mounting of semiconductor chip Pending JPS6425429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62180997A JPS6425429A (en) 1987-07-22 1987-07-22 Mounting of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62180997A JPS6425429A (en) 1987-07-22 1987-07-22 Mounting of semiconductor chip

Publications (1)

Publication Number Publication Date
JPS6425429A true JPS6425429A (en) 1989-01-27

Family

ID=16092927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62180997A Pending JPS6425429A (en) 1987-07-22 1987-07-22 Mounting of semiconductor chip

Country Status (1)

Country Link
JP (1) JPS6425429A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379562B1 (ko) * 2001-02-15 2003-04-10 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 플립칩 본딩방법
CN103065990A (zh) * 2012-12-12 2013-04-24 山西国惠光电科技有限公司 一种晶圆级倒装互联方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379562B1 (ko) * 2001-02-15 2003-04-10 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 플립칩 본딩방법
CN103065990A (zh) * 2012-12-12 2013-04-24 山西国惠光电科技有限公司 一种晶圆级倒装互联方法

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