JPS6425267A - Data transfer confirming system - Google Patents
Data transfer confirming systemInfo
- Publication number
- JPS6425267A JPS6425267A JP18208187A JP18208187A JPS6425267A JP S6425267 A JPS6425267 A JP S6425267A JP 18208187 A JP18208187 A JP 18208187A JP 18208187 A JP18208187 A JP 18208187A JP S6425267 A JPS6425267 A JP S6425267A
- Authority
- JP
- Japan
- Prior art keywords
- data
- dma
- completion signal
- command
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To reduce cost by generating data for a data confirming command used in a pair with a line data transfer requesting command with a data generating means provided on an interface circuit through the use of a DMA completion signal and data completion signal. CONSTITUTION:The data in the memory of an input output device 104 is DMA- transferred to a main memory 102 on a host side by a line data transfer requesting command from a host CPU 101. In such a case, based on a DMA transfer completion signal on a common bus interface 103 for the line data transfer requesting command previously executed and the data completion signal (flame end) which goes to a DMA transfer completion within a byte length at the time of DMA transfer, a data generating means 105 generates the data for response for a data confirming command which forms a pair with the line data transfer requesting command, and sends it back to the host CPU 101.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18208187A JPH0721787B2 (en) | 1987-07-21 | 1987-07-21 | Data transfer confirmation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18208187A JPH0721787B2 (en) | 1987-07-21 | 1987-07-21 | Data transfer confirmation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6425267A true JPS6425267A (en) | 1989-01-27 |
JPH0721787B2 JPH0721787B2 (en) | 1995-03-08 |
Family
ID=16112021
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18208187A Expired - Lifetime JPH0721787B2 (en) | 1987-07-21 | 1987-07-21 | Data transfer confirmation method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0721787B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9860315B2 (en) | 1998-09-10 | 2018-01-02 | International Business Machines Corporation | Controlling the state of duplexing of coupling facility structures |
-
1987
- 1987-07-21 JP JP18208187A patent/JPH0721787B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9860315B2 (en) | 1998-09-10 | 2018-01-02 | International Business Machines Corporation | Controlling the state of duplexing of coupling facility structures |
Also Published As
Publication number | Publication date |
---|---|
JPH0721787B2 (en) | 1995-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6425267A (en) | Data transfer confirming system | |
DE3277424D1 (en) | Coupler for processors | |
JPS56110125A (en) | Data processing device | |
JPS5674725A (en) | Computer system | |
JPS5644925A (en) | Control system of data processing system | |
KR950003659B1 (en) | Asynchronous transmission device fitting for small computer system interface | |
JPS54101235A (en) | Operational processor | |
JPS57114925A (en) | Hold control system | |
JPS5491156A (en) | Data processing system | |
JPS5419628A (en) | Duplex micro computer system | |
JPS5685176A (en) | Picture data compressing device | |
JPS5685177A (en) | Picture data expanding device | |
JPS55157027A (en) | Input and output transfer control unit | |
JPS57199040A (en) | Synchronizing device for data transfer | |
JPS5478639A (en) | Input/output control unit | |
JPS57174723A (en) | Bus load controlling system | |
JPS5597627A (en) | On-line terminal control unit | |
JPS5567819A (en) | Input/output control system | |
JPS54101631A (en) | Bus control system | |
JPS6441951A (en) | Dma controller | |
JPS57137921A (en) | Interface device | |
JPS553047A (en) | Microdiagnosis system | |
KR940003307A (en) | Board-to-board data transfer device using 1 byte latch | |
JPS57150017A (en) | Direct memory access system | |
JPS53103332A (en) | Input/output control system for information processor |