JPS6425265A - System for packing peripheral circuit control program - Google Patents

System for packing peripheral circuit control program

Info

Publication number
JPS6425265A
JPS6425265A JP62182781A JP18278187A JPS6425265A JP S6425265 A JPS6425265 A JP S6425265A JP 62182781 A JP62182781 A JP 62182781A JP 18278187 A JP18278187 A JP 18278187A JP S6425265 A JPS6425265 A JP S6425265A
Authority
JP
Japan
Prior art keywords
peripheral circuit
control program
program data
microprocessor
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62182781A
Other languages
Japanese (ja)
Inventor
Osamu Yamato
Ikuhiro Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62182781A priority Critical patent/JPS6425265A/en
Publication of JPS6425265A publication Critical patent/JPS6425265A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To shorten a working man-hour by providing a control program loading means which loads a control program stored in an auxiliary storage device at the time of starting an operation to a RAM in each peripheral circuit. CONSTITUTION:In an initial setting procedure, a microprocessor 11 of a peripheral circuit 1 requests the reading and transfer of the control program data for the peripheral circuit 1 stored in an FD 25 for a peripheral circuit 2. A microprocessor 21 of a peripheral circuit 2 receives the request of the transfer with a bus interface circuit 24, controls the FD 25, reads out corresponding control program data, and transfers these through the control bus interface circuit 24 and a control bus 5 to the peripheral circuit 1. The microprocessor 11 of the peripheral circuit 1 receives the control program data, loads them to a RAM 13, combines the control program data on a PROM 12 and the RAM 13, and controls the peripheral circuit 1.
JP62182781A 1987-07-21 1987-07-21 System for packing peripheral circuit control program Pending JPS6425265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62182781A JPS6425265A (en) 1987-07-21 1987-07-21 System for packing peripheral circuit control program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62182781A JPS6425265A (en) 1987-07-21 1987-07-21 System for packing peripheral circuit control program

Publications (1)

Publication Number Publication Date
JPS6425265A true JPS6425265A (en) 1989-01-27

Family

ID=16124308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62182781A Pending JPS6425265A (en) 1987-07-21 1987-07-21 System for packing peripheral circuit control program

Country Status (1)

Country Link
JP (1) JPS6425265A (en)

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