JPS642420A - Data transfer circuit - Google Patents

Data transfer circuit

Info

Publication number
JPS642420A
JPS642420A JP15832787A JP15832787A JPS642420A JP S642420 A JPS642420 A JP S642420A JP 15832787 A JP15832787 A JP 15832787A JP 15832787 A JP15832787 A JP 15832787A JP S642420 A JPS642420 A JP S642420A
Authority
JP
Japan
Prior art keywords
data
register
shift register
reads
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15832787A
Other languages
Japanese (ja)
Other versions
JPH012420A (en
Inventor
Takumi Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62-158327A priority Critical patent/JPH012420A/en
Priority claimed from JP62-158327A external-priority patent/JPH012420A/en
Publication of JPS642420A publication Critical patent/JPS642420A/en
Publication of JPH012420A publication Critical patent/JPH012420A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To shorten the program processing time of a data processor by sending data in series while inspecting their variation, one by one, by a 1st shift register and an exclusive OR gate, and interrupting a data processor when a reception- side detecting and holding circuit detects a dissident bit in the data. CONSTITUTION:Parallel data 8 which are read in a parallel-series (PS) shift register 9 previously with data transfer timing 5 are outputted, one by one, to the EXOR gate 21 and S shift register 20. The data register 12 reads in the data of an SP shift register 11 with a next data transfer start signal 4 and a DFF 23 reads in the dissident bit detection result of a JKFF 22 and interrupts the data processor 15. The data processor 15 outputs a gate signal to the data register 12, reads in parallel data 14 outputted by the data register 12, and performs data detection processing for detecting variation data. The data processor, therefore, need not read new data unnecessarily and the program processing time is shortened.
JP62-158327A 1987-06-25 data transfer circuit Pending JPH012420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-158327A JPH012420A (en) 1987-06-25 data transfer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-158327A JPH012420A (en) 1987-06-25 data transfer circuit

Publications (2)

Publication Number Publication Date
JPS642420A true JPS642420A (en) 1989-01-06
JPH012420A JPH012420A (en) 1989-01-06

Family

ID=

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7183886B2 (en) 2003-03-28 2007-02-27 Sumida Technologies Incorporated Inductance device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7183886B2 (en) 2003-03-28 2007-02-27 Sumida Technologies Incorporated Inductance device

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