JPS5478002A - Additional bit removal system - Google Patents

Additional bit removal system

Info

Publication number
JPS5478002A
JPS5478002A JP14557077A JP14557077A JPS5478002A JP S5478002 A JPS5478002 A JP S5478002A JP 14557077 A JP14557077 A JP 14557077A JP 14557077 A JP14557077 A JP 14557077A JP S5478002 A JPS5478002 A JP S5478002A
Authority
JP
Japan
Prior art keywords
synchronizing
data
fields
circuit
receiving data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14557077A
Other languages
Japanese (ja)
Inventor
Chiaki Motegi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14557077A priority Critical patent/JPS5478002A/en
Publication of JPS5478002A publication Critical patent/JPS5478002A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To simplify a circuit constitution with performing the detection of synchronizing fields and the removal of additional bits for serial data in the same circuit, by detecting the continuity of prescribed bits of receiving data. CONSTITUTION:Receiving data 11a is given to the input side of additional bit removing circuit 11 synchronously with reciving synchronizing clock 11b, and synchronizing fields are preferencially detected to output synchronizing field detection signal 11c, and output data 11d with additional bits of information fields removed is successively given to the input side of data register 12 synchronously with data clock 11e. In this case, the detection of synchronizing fields and the removal of additional bits are performed by a counter, which count continuities of ''0'' or ''1'' of receiving data 11a, and a count number decoder in circuit 11.
JP14557077A 1977-12-03 1977-12-03 Additional bit removal system Pending JPS5478002A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14557077A JPS5478002A (en) 1977-12-03 1977-12-03 Additional bit removal system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14557077A JPS5478002A (en) 1977-12-03 1977-12-03 Additional bit removal system

Publications (1)

Publication Number Publication Date
JPS5478002A true JPS5478002A (en) 1979-06-21

Family

ID=15388163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14557077A Pending JPS5478002A (en) 1977-12-03 1977-12-03 Additional bit removal system

Country Status (1)

Country Link
JP (1) JPS5478002A (en)

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