JPS6423652A - Data buffer circuit - Google Patents

Data buffer circuit

Info

Publication number
JPS6423652A
JPS6423652A JP17950387A JP17950387A JPS6423652A JP S6423652 A JPS6423652 A JP S6423652A JP 17950387 A JP17950387 A JP 17950387A JP 17950387 A JP17950387 A JP 17950387A JP S6423652 A JPS6423652 A JP S6423652A
Authority
JP
Japan
Prior art keywords
interruption
signal
cpu
generating
counter circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17950387A
Other languages
Japanese (ja)
Inventor
Manabu Niiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17950387A priority Critical patent/JPS6423652A/en
Publication of JPS6423652A publication Critical patent/JPS6423652A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent data omission from generating, by providing a means which generates two kinds of interruptions having different priority and, when a 1st interruption is not accepted, generating a 2nd interruption. CONSTITUTION:This data buffer circuit is provided with a CPU 10, latch section 20, shift register section 30, counter circuit 40, and an interruption generating section 50 which generates two kinds of interruptions having different priority to the CPU 10 in accordance with a signal RC of the counter circuit 40. When the prescribed signal RC is generated from the counter circuit 40 an interruption is requested to the CPU 10 by using the 1st interruption signal having the lower priority to the CPU 10 and, when the interruption by means of the 1st interruption signal is not accepted, the interruption request is again performed by using the 2nd interruption signal having the higher priority. Therefore, data writing is certainly carried out and the occurrence of data omission can be prevented.
JP17950387A 1987-07-17 1987-07-17 Data buffer circuit Pending JPS6423652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17950387A JPS6423652A (en) 1987-07-17 1987-07-17 Data buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17950387A JPS6423652A (en) 1987-07-17 1987-07-17 Data buffer circuit

Publications (1)

Publication Number Publication Date
JPS6423652A true JPS6423652A (en) 1989-01-26

Family

ID=16066952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17950387A Pending JPS6423652A (en) 1987-07-17 1987-07-17 Data buffer circuit

Country Status (1)

Country Link
JP (1) JPS6423652A (en)

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