JPS6423650A - Interface circuit - Google Patents

Abstract

PURPOSE:To reduce a load on a central processing unit to quickly interface the processing unit unconsciously of the switching of a signal form, by setting the signal form in advance by means of the central processing unit and, when signals are received by the set signal form, sending the signals to the central processing unit after converting all of the signals into NRZ signals. CONSTITUTION:When a data string formed of a leading section of NRZ signals of 2S bits/sec. in transmitting speed and the succeeding section of SPL (split phase) signals of A bits/sec. in transmitting speed is taken into the CPU 20, it is set at the CPU 20 that by which signal form the data string is taken in. Then an interruption generating means 40 and data converting means 50 are actuated in accordance with the set content and the data are taken in from a data storing means 60, in which the NRZ signals and SPL signals are stored, with the SPL signals being stored after they are converted into NRZ signals at every other bit. Therefore, the software load in the CPU 20 can be reduced and an interface circuit 10 which can cope with a high-speed process by the CPU 20 can be realized.