JPS6423338A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS6423338A
JPS6423338A JP18049387A JP18049387A JPS6423338A JP S6423338 A JPS6423338 A JP S6423338A JP 18049387 A JP18049387 A JP 18049387A JP 18049387 A JP18049387 A JP 18049387A JP S6423338 A JPS6423338 A JP S6423338A
Authority
JP
Japan
Prior art keywords
circuit
packet
priority order
output
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18049387A
Other languages
Japanese (ja)
Other versions
JP2522951B2 (en
Inventor
Kazuyuki Tanaka
Masahisa Shimizu
Hiroki Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62180493A priority Critical patent/JP2522951B2/en
Publication of JPS6423338A publication Critical patent/JPS6423338A/en
Application granted granted Critical
Publication of JP2522951B2 publication Critical patent/JP2522951B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To simplify a hardware structure by transferring data to one of two register rings from the other via a data transmission line. CONSTITUTION:When an interface control circuit IFC decides that a data holding circuit 1 contains no packet, the output of a data holding circuit 2 set at the other side is selected and executed based on the output of a comparator 6. When the circuit 1 contains a packet, the execution of the circuit 1 is carried out regardless of the presence or absence of a packet in the circuit 2 since the priority order of the circuit 1 is higher than the circuit 2. Thus the clock is stopped at the side of a processing module having a low priority order when both circuits 1 and 2 contain the packets and the outputs of two comparators 5 and 6 are coincident and conflicting with each other.
JP62180493A 1987-07-20 1987-07-20 Interface circuit Expired - Lifetime JP2522951B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62180493A JP2522951B2 (en) 1987-07-20 1987-07-20 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62180493A JP2522951B2 (en) 1987-07-20 1987-07-20 Interface circuit

Publications (2)

Publication Number Publication Date
JPS6423338A true JPS6423338A (en) 1989-01-26
JP2522951B2 JP2522951B2 (en) 1996-08-07

Family

ID=16084201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62180493A Expired - Lifetime JP2522951B2 (en) 1987-07-20 1987-07-20 Interface circuit

Country Status (1)

Country Link
JP (1) JP2522951B2 (en)

Also Published As

Publication number Publication date
JP2522951B2 (en) 1996-08-07

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