JPS57201953A - Information transmitting method of multiple cpu system - Google Patents

Information transmitting method of multiple cpu system

Info

Publication number
JPS57201953A
JPS57201953A JP56085979A JP8597981A JPS57201953A JP S57201953 A JPS57201953 A JP S57201953A JP 56085979 A JP56085979 A JP 56085979A JP 8597981 A JP8597981 A JP 8597981A JP S57201953 A JPS57201953 A JP S57201953A
Authority
JP
Japan
Prior art keywords
control systems
circuits
coupled
control system
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56085979A
Other languages
Japanese (ja)
Inventor
Kenji Hiramine
Reijiro Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP56085979A priority Critical patent/JPS57201953A/en
Publication of JPS57201953A publication Critical patent/JPS57201953A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Abstract

PURPOSE:To simplify an interchange of information among control systems, by interchanging information invariably according to a certain information interchange procedure without discriminating between the normal state and abnormal state of each control system circuit of an information processing control system. CONSTITUTION:The control system A and control system B of a multiple CPU system are coupled by circuits a1 and a2, the control systems A and C are coupled by circuits b1 and b2, and the control systems C and D are coupled by circuits C1 and C2; and the control systems D and B are coupled by circuits d1 and d2, and the control systems B and C are coupled by circuits e1 and e2, and the control systems A and D are coupled by circuits f1 and f2. Transmission between control systems employs a full duplex system, and from the control system A to the control system B, data frames C and D are transmitted in addition to a data frame A generated at the control system A. Transmission from other control systems is the same, and a data frame other than data generated at a transmission destination is transmitted to other control systems.
JP56085979A 1981-06-03 1981-06-03 Information transmitting method of multiple cpu system Pending JPS57201953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56085979A JPS57201953A (en) 1981-06-03 1981-06-03 Information transmitting method of multiple cpu system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56085979A JPS57201953A (en) 1981-06-03 1981-06-03 Information transmitting method of multiple cpu system

Publications (1)

Publication Number Publication Date
JPS57201953A true JPS57201953A (en) 1982-12-10

Family

ID=13873821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56085979A Pending JPS57201953A (en) 1981-06-03 1981-06-03 Information transmitting method of multiple cpu system

Country Status (1)

Country Link
JP (1) JPS57201953A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008209113A (en) * 2007-02-23 2008-09-11 Toyo Seiki Seisakusho:Kk Test piece supply device of impact resilience testing machine
US9759641B2 (en) 2009-11-27 2017-09-12 Hysitron, Inc. Micro electro-mechanical heater
US9804072B2 (en) 2011-11-28 2017-10-31 Hysitron, Inc. High temperature heating system
US9829417B2 (en) 2012-06-13 2017-11-28 Hysitron, Inc. Environmental conditioning assembly for use in mechanical testing at micron or nano-scales

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008209113A (en) * 2007-02-23 2008-09-11 Toyo Seiki Seisakusho:Kk Test piece supply device of impact resilience testing machine
US9759641B2 (en) 2009-11-27 2017-09-12 Hysitron, Inc. Micro electro-mechanical heater
US9804072B2 (en) 2011-11-28 2017-10-31 Hysitron, Inc. High temperature heating system
US10241017B2 (en) 2011-11-28 2019-03-26 Bruker Nano, Inc. High temperature heating system
US9829417B2 (en) 2012-06-13 2017-11-28 Hysitron, Inc. Environmental conditioning assembly for use in mechanical testing at micron or nano-scales

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