JPS6411438A - Multiple address communication circuit with confirmation answer - Google Patents

Multiple address communication circuit with confirmation answer

Info

Publication number
JPS6411438A
JPS6411438A JP16755587A JP16755587A JPS6411438A JP S6411438 A JPS6411438 A JP S6411438A JP 16755587 A JP16755587 A JP 16755587A JP 16755587 A JP16755587 A JP 16755587A JP S6411438 A JPS6411438 A JP S6411438A
Authority
JP
Japan
Prior art keywords
multiple address
address
reception
answer
confirmation answer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16755587A
Other languages
Japanese (ja)
Inventor
Teiichi Ishido
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16755587A priority Critical patent/JPS6411438A/en
Publication of JPS6411438A publication Critical patent/JPS6411438A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To detect an abnormal answer in group units and to limit an opposite part to which a signal is resent back by informing the result of multiple address from plural multiple address reception-side circuits on the multiple address transmission-side circuit by every group based upon the number of address buses. CONSTITUTION:In an example where 2N-1 processing modes are added for N address buses, a figure shows {(2<3>-1)divided by 3} 2.3, so three confirmation answer signals are sent through each address bus and three groups are formed. This method is realized by the wired-OR format of an collector output. Thus, confirmation answer data sent out to the address bus are fetched to the multiple address answer receiving circuit 9 of the multiple address transmission-side circuit 5 at the 1 0 timing of BAK. On the multiple address transmission side, abnormality of some reception processing module is detected, three by three, from the reception result if the abnormality occurs to enable reaction such as resending to the processing module which has perfomed the abnormal reception.
JP16755587A 1987-07-03 1987-07-03 Multiple address communication circuit with confirmation answer Pending JPS6411438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16755587A JPS6411438A (en) 1987-07-03 1987-07-03 Multiple address communication circuit with confirmation answer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16755587A JPS6411438A (en) 1987-07-03 1987-07-03 Multiple address communication circuit with confirmation answer

Publications (1)

Publication Number Publication Date
JPS6411438A true JPS6411438A (en) 1989-01-17

Family

ID=15851894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16755587A Pending JPS6411438A (en) 1987-07-03 1987-07-03 Multiple address communication circuit with confirmation answer

Country Status (1)

Country Link
JP (1) JPS6411438A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006270447A (en) * 2005-03-23 2006-10-05 Canon Inc System and method for broadcast communication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006270447A (en) * 2005-03-23 2006-10-05 Canon Inc System and method for broadcast communication

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