JPH05303537A - Multi-address communication circuit - Google Patents

Abstract

PURPOSE:To receive a reception-side confirmation answer on a transmission side at the time of a multi-address communication, to shorten the communication time and decrease common bus lines, and to limit retransmission as reaction to only one destination. CONSTITUTION:A multi-address transmission-side circuit 5 once obtaining the right to use a common bus 3 outputs a multi-address from a multi-address generating circuit 10 to an address bus 7, adds a parity bit from a parity generating circuit 12 to three bytes of registers 13-15, and sends them out to a data bus 8. A multi-address reception-side circuit 4 fetches the multi-address by a multi-address detecting circuit 16 and outputs a detection signal, and a receiver 17 fetches the three following byte data and stores them in registers 20-22. A parity check circuit 18 makes a parity check. An AND circuit 19 with open- collector output inputs a control signal, a parity check signal, and a the detection signal and outputs a confirmation response signal to the address bus 7 at the timing of the transition of BAK from '1' to '0'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a broadcast communication circuit in a distributed processing system in which a plurality of processing modules are connected by a common bus.

[0002]

2. Description of the Related Art Conventionally, in this type of broadcast communication, there are a first system that does not make a confirmation response and a second system that makes a confirmation response. Method in which the receiving side module sequentially transmits to the transmitting side module in time series, and a method in which the receiving side module is grouped by using a dedicated signal line or address line and the acknowledgment is collectively transmitted to the transmitting side module. (For example, Japanese Patent Application No. 62-167555).

[0003]

The above-mentioned first conventional system has a problem that it cannot be confirmed whether or not the broadcast communication can be reliably executed. Further, in the former method of the second system, since a response for confirmation is received from each reception processing module in time series, considerable time is required. On the other hand, of the latter methods, the method using a dedicated signal line has a drawback that the number of signal lines for connecting between processing modules is increased and the number of circuits is also increased. On the other hand, in the method of grouping the receiving side modules using an address line or the like and transmitting the confirmation response in a lump, when the number of processing modules in the system increases, the number of processing modules of the confirmation response source notified by one signal line increases. When the number of packets increases and retransmission is performed when an abnormality occurs, another processing module belonging to the same group as the module in which the abnormality has occurred will receive the same broadcast again. If the number of processing modules per group increases, an extra retransmission operation is performed, and the processing modules that have been re-received have the drawback of discarding broadcast data.

[0004]

SUMMARY OF THE INVENTION A broadcast communication circuit of the present invention has a plurality of processing modules and an address bus for displaying an address indicating a destination or a broadcast, for communicating between the processing modules. Distributed bus system including a common bus and an arbiter circuit for controlling contention of a common bus use right between the processing modules, and performing broadcast communication from one processing module to a plurality of other processing modules by a broadcast address. In the broadcast communication circuit in the above, one control signal line for displaying the timing for sending the confirmation response result, and whether the reception was normally or abnormally performed in the broadcast communication to each of the plurality of processing modules A broadcast receiving side circuit for outputting the result to a predetermined one of the address buses at the timing of the control signal, and a plurality of the receiving side processes A broadcast transmission side circuit for receiving the confirmation response result from the address bus from the address bus, dividing the plurality of processing modules into groups corresponding to the number of the address buses, and each processing module in each group. Different acknowledgment response result transmission timings are assigned to each of the processing modules, and each processing module sends an acknowledgment response result to one address bus line corresponding to the group to which the processing module belongs at the timing corresponding to the processing module in the group. It is characterized in that it is notified by time division multiplexing.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 3 is a block diagram of a distributed processing system showing an application example of the broadcast communication circuit of the present invention.

A large number of logic modules (hereinafter referred to as LM) 1a to 1n are connected via a common bus 3. A common bus arbiter circuit (hereinafter referred to as AB to prevent transmission right conflict)
T) 2 is provided. The broadcast receiving side circuit and the broadcast transmitting side circuit which constitute the broadcast communication circuit according to the present invention are each LM1.
a, 1n.

FIG. 1 is a block diagram of a processing module showing an embodiment of a broadcast communication circuit of the present invention, showing a broadcast receiving side circuit and a broadcast transmitting side circuit provided in one processing module. The common bus 3 is composed of a control signal bus 6, an address bus 7 and a data bus 8. FIG. 1 shows an example of broadcasting 3-byte data via the common bus 3. FIG. 2 shows a time chart for explaining the operation of the circuit in FIG.

In explaining the operation of the broadcast communication of this embodiment, the broadcast transmitting side circuit 5 of FIG. 1 is used as the broadcast transmitting side circuit of the transmitting side processing module, and the broadcast receiving side circuit 4 is used as one receiving side circuit. explain.

The broadcast transmission side circuit 5, as shown in FIG.
When the right to use the common bus 3 is acquired by RQ and BAK,
The broadcast address generation circuit 10 outputs the broadcast address to the address bus 7 of the common bus 3. Then, after that, a parity bit generated by the parity generation circuit 12 is added to the 3-byte data accumulated in the registers 13 to 15, and the data is sent to the data bus 8 via the driver 11.

In the broadcast receiving side circuit 4, the broadcast address detecting circuit 16 fetches the broadcast address on the address bus 7, compares it with the address value, detects that it is a broadcast address, and outputs a detection signal. .. This detection signal is sent to one of the AND circuits 19 with open collector output and the receiver 17. Upon receiving the detection signal, the receiver 17 takes in 3 bytes of data which is subsequently sent onto the data bus 8. And the first 1-byte data is register 2
0, the next 1-byte data is stored in the register 21, the last 1
The byte data is stored in the register 22, respectively. At this time, the parity signal added to the data is also taken into the parity check circuit 18 and the parity check is performed. Since the control signal of the control signal bus 6, the signal indicating the result of the parity check and the above detection signal are input to the input of the AND circuit 19 with open collector output, B
The normal / abnormal result is sent from the AND circuit 19 with open collector output to the address bus 7 as a confirmation response signal at the timing when AK is “1” → “0”.

FIG. 4 is a block diagram showing an example of outputting the response result to the address bus in the broadcast receiving side circuit in FIG.
An example is shown in which (2N-1) processing modules are added to N address buses. Where {(2 ** N-
1) ÷ N)} is rounded up to an integer and M is 1
The address bus of the book can carry M acknowledgment signals. In this embodiment, one address carries M = 3 confirmation response signals to form three groups.

Time-division-multiplexing the acknowledgment signals of the three processing modules on one address bus means that the acknowledgment timing generation circuit 23 in the broadcast transmission side circuit 5 outputs a response via the driver 24. It is realized by sequentially loading the data on the address bus 7 in synchronization with the confirmation return timing signal bus 25. That is, in the broadcast receiving side circuit 4, the response confirmation return timing signal 25 is "1" → "0".
When the counter value changes, the counting circuit 26 counts, and the count value is compared with the module number 27 by the comparison circuit 28.
The result of the parity check is output from the AND circuit with output 19 to the address bus 7 at the timing when the comparison results match. In the acknowledgment data thus sent to the address bus, the acknowledgment response timing is "0" →
It is taken into the broadcast response receiving circuit 9 of the broadcast transmitting side circuit 5 at the timing of "1".

On the broadcast transmission side, if there is an abnormality in any of the receiving modules based on the reception result, this can be detected in units of processing modules, and it can be retransmitted only to the abnormal reception processing module. Reaction is possible.

[0014]

As described above, according to the present invention, the transmitting side can receive the acknowledgment of the receiving side during the broadcast communication. Further, since the confirmation response is received once within the broadcast communication time, the communication time can be reduced. Further, since the confirmation response is communicated by the address bus, it is not necessary to provide a dedicated line for response, and the number of common bus lines can be reduced. Furthermore, since an abnormal response can be detected for each processing module, there is an effect that the retransmission partner as a reaction can be uniquely limited.

[Brief description of drawings]

FIG. 1 is a block diagram of a processing module showing an embodiment of a broadcast communication circuit of the present invention.

FIG. 2 is a time chart for explaining the operation of the circuit in FIG.

FIG. 3 is a block diagram of a distributed processing system showing an application example of the broadcast communication circuit of the present invention.

4 is a block diagram showing an example of outputting a response result to an address bus in the broadcast receiving side circuit in FIG. 1. FIG.

[Explanation of symbols]

1a, 1n, 23a, 23n Processing module (LM) 2 Common bus arbiter circuit (ABT) 3 Common bus 4 Broadcast receiving side circuit 5 Broadcast transmitting side circuit 6 Control signal bus 7 Address bus 8 Data bus 9 Broadcast response Reception circuit 10 Broadcast address generation circuit 11,24 Driver 12 Parity generation circuit 13, ~ 15, 20, ~ 22 register 16 Broadcast address detection circuit 17 Receiver 18 Parity check circuit 19 AND circuit with open collector output 23 Confirmation response return timing Generation circuit 24a to 24n Open collector circuit for confirmation response output 25 Confirmation response timing signal line 26 Counting circuit 27 Module number 28 Comparison circuit

Claims (1)

[Claims] 1. A common bus for communicating between the processing modules, which comprises a plurality of processing modules, an address bus for displaying an address meaning a destination or a broadcast, and a common bus between the processing modules. Equipped with an arbiter circuit that controls contention rights, 1 by broadcast address
In a broadcast communication circuit in a distributed processing system for performing broadcast communication from one processing module to a plurality of other processing modules, one control signal line for displaying a timing for sending an acknowledgment response result, and a plurality of the processings. A broadcast receiving side circuit for outputting to each of the modules whether or not the reception is normally or abnormally received at a predetermined one of the address buses at the timing of the control signal; A broadcast transmission side circuit that receives the acknowledgment results from the plurality of processing modules from the address bus is provided, and the plurality of processing modules are divided into groups corresponding to the number of the address buses. Different confirmation response result transmission timings are assigned to the processing modules, and the processing modules Broadcast circuits and notifies time-division multiplexing the acknowledgment result at a timing corresponding to the processing module in the group for one address bus line corresponding to the group to be.