JPS6423136U - - Google Patents

Info

Publication number
JPS6423136U
JPS6423136U JP1987117821U JP11782187U JPS6423136U JP S6423136 U JPS6423136 U JP S6423136U JP 1987117821 U JP1987117821 U JP 1987117821U JP 11782187 U JP11782187 U JP 11782187U JP S6423136 U JPS6423136 U JP S6423136U
Authority
JP
Japan
Prior art keywords
nonvolatile memory
operating mode
circuit
input
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987117821U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987117821U priority Critical patent/JPS6423136U/ja
Priority to KR1019880008656A priority patent/KR910008450B1/en
Publication of JPS6423136U publication Critical patent/JPS6423136U/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Electronic Switches (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Read Only Memory (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路構成図、
第２図は従来のＬＳＩ回路におけるモード設定動
作を説明するための図である。 １１……ＬＳＩ回路、１２……論理回路、１３
……不揮発性メモリ、１４１〜１４ｎ……データ
入力端子、１５……テスト信号入力端子、１６１
〜１６ｎ……出力端子、１７１〜１７ｎ……入力
キー、１８……テストキー。 FIG. 1 is a circuit diagram showing an embodiment of the present invention;
FIG. 2 is a diagram for explaining a mode setting operation in a conventional LSI circuit. 11...LSI circuit, 12...Logic circuit, 13
...Nonvolatile memory, 14 1 to 14n... Data input terminal, 15... Test signal input terminal, 16 1
 ~16n...Output terminal, 171 ~17n...Input key, 18...Test key.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力用及び出力用の端子を備え、複数の動作モ
ードを有するＬＳＩ回路において、動作モードを
記憶する書換え可能な不揮発性メモリと、前記入
力用端子を介して前記不揮発性メモリに動作モー
ドを書込む手段とを具備したことを特徴とするＬ
ＳＩ回路。 In an LSI circuit equipped with input and output terminals and having a plurality of operating modes, a rewritable nonvolatile memory stores an operating mode, and the operating mode is written in the nonvolatile memory via the input terminal. L characterized by comprising means.
SI circuit.
JP1987117821U 1987-07-31 1987-07-31 Pending JPS6423136U (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1987117821U JPS6423136U (en) 1987-07-31 1987-07-31
KR1019880008656A KR910008450B1 (en) 1987-07-31 1988-07-12 Lsi mode setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987117821U JPS6423136U (en) 1987-07-31 1987-07-31

Publications (1)

Publication Number Publication Date
JPS6423136U true JPS6423136U (en) 1989-02-07

Family

ID=31361613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987117821U Pending JPS6423136U (en) 1987-07-31 1987-07-31

Country Status (2)

Country Link
JP (1) JPS6423136U (en)
KR (1) KR910008450B1 (en)

Also Published As

Publication number Publication date
KR890002780A (en) 1989-04-11
KR910008450B1 (en) 1991-10-15

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