JPS6419856A - Serial transmission system - Google Patents

Serial transmission system

Info

Publication number
JPS6419856A
JPS6419856A JP63010554A JP1055488A JPS6419856A JP S6419856 A JPS6419856 A JP S6419856A JP 63010554 A JP63010554 A JP 63010554A JP 1055488 A JP1055488 A JP 1055488A JP S6419856 A JPS6419856 A JP S6419856A
Authority
JP
Japan
Prior art keywords
control
section
bit
message
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63010554A
Other languages
Japanese (ja)
Other versions
JPH0467827B2 (en
Inventor
Burutsukusu Etsukaato Aruton
Henrii Soodaabaagu Jiyon
Bii Matsukufuigansu Robaato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pitney Bowes Inc
Original Assignee
Pitney Bowes Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pitney Bowes Inc filed Critical Pitney Bowes Inc
Priority to JP63010554A priority Critical patent/JPS6419856A/en
Publication of JPS6419856A publication Critical patent/JPS6419856A/en
Publication of JPH0467827B2 publication Critical patent/JPH0467827B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To provide a distribute processing unit separating safe data from unsafe data and generating and printing out a postal rate by providing a franking machine having two units or over each with computer control so as to provide communication between the units. CONSTITUTION: A franking machine 20 has a control section 75, an accounting section 57 and a print section 56, each section is provided with a CPU and with a crystal control clock. The communication between the sections is based on a serial message sent/received asynchronously and a format and bit timing are set accurately to warrant the synchronous transmission and reception. Furthermore, in the case of receiving a 1st bit of the transmission message, the received bit is sent back from the receiver to a transmitter for the comparison to attain proving of the validity of the message at a minimum time period in succession to the transmission of all messages. A total control and data signal is sent by using the conductor of a same pair in each direction in a timing decided accurately for the control.
JP63010554A 1988-01-20 1988-01-20 Serial transmission system Granted JPS6419856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63010554A JPS6419856A (en) 1988-01-20 1988-01-20 Serial transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63010554A JPS6419856A (en) 1988-01-20 1988-01-20 Serial transmission system

Publications (2)

Publication Number Publication Date
JPS6419856A true JPS6419856A (en) 1989-01-23
JPH0467827B2 JPH0467827B2 (en) 1992-10-29

Family

ID=11753472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63010554A Granted JPS6419856A (en) 1988-01-20 1988-01-20 Serial transmission system

Country Status (1)

Country Link
JP (1) JPS6419856A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50103203A (en) * 1974-01-07 1975-08-15

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50103203A (en) * 1974-01-07 1975-08-15

Also Published As

Publication number Publication date
JPH0467827B2 (en) 1992-10-29

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