JPS6418757U - - Google Patents
Info
- Publication number
- JPS6418757U JPS6418757U JP11427787U JP11427787U JPS6418757U JP S6418757 U JPS6418757 U JP S6418757U JP 11427787 U JP11427787 U JP 11427787U JP 11427787 U JP11427787 U JP 11427787U JP S6418757 U JPS6418757 U JP S6418757U
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- film
- substrate
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010408 film Substances 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 2
- 150000003377 silicon compounds Chemical class 0.000 claims 3
- 229920002120 photoresistant polymer Polymers 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Description
第１図は本考案の一実施例に係る薄膜トランジ
スタの構造を示す図、第２図ａ〜ｄは本考案の薄
膜トランジスタの第一実施例に係る製造工程を示
す図、第３図ａ〜ｄは本考案の薄膜トランジスタ
の第二実施例に係る製造工程を示す図、第４図ａ
〜ｃは従来の薄膜トランジスタの製造工程を示す
図である。
１１……基板、１２……ゲート電極、１３……
ＳＯＧ膜、１４……ゲート絶縁膜、１５……半導
体膜、１７……ソース電極、１８……ドレイン電
極。
FIG. 1 is a diagram showing the structure of a thin film transistor according to an embodiment of the present invention, FIGS. 2 a to d are diagrams showing the manufacturing process according to the first embodiment of the thin film transistor of the present invention, and FIGS. A diagram showing the manufacturing process according to the second embodiment of the thin film transistor of the present invention, FIG. 4a
-c are diagrams showing the manufacturing process of a conventional thin film transistor. 11...Substrate, 12...Gate electrode, 13...
SOG film, 14... gate insulating film, 15... semiconductor film, 17... source electrode, 18... drain electrode.
補正 昭６２．１１．４
図面の簡単な説明を次のように補正する。
明細書第１３頁第１０行目に「ソース」とある
を「ドレイン」と補正する。
明細書第１３頁第１１行目に「ドレイン」とあ
るを「ソース」と補正する。Amendment November 4, 1982 The brief description of the drawing is amended as follows. In the 10th line of page 13 of the specification, the word "source" is corrected to read "drain." In the 11th line of page 13 of the specification, the word "drain" is corrected to read "source."
Claims (1)
面上のゲート電極が形成された部分以外の部分に
けい素化合物の塗布、焼成によつて前記ゲート電
極の膜厚とほぼ等しい膜厚に形成された平坦化絶
縁膜と、少なくとも前記ゲート電極面上に形成さ
れたゲート絶縁膜と、このゲート絶縁膜に順次形
成された半導体膜、及びソース、ドレイン電極と
を具備していることを特徴とする薄膜トランジス
タ。 (2) 前記平坦化絶縁膜は、前記基板及びゲート
電極上にけい素化合物を塗布し、焼成後、該ゲー
ト電極の表面が露出する程度のエツチングにより
形成されていることを特徴とする実用新案登録請
求の範囲第１項記載の薄膜トランジスタ。 (3) 前記平坦化絶縁膜は、けい素化合物の溶液
を前記基板及びフオトレジストで被つたゲート電
極上に塗布し被膜を形成した後、前記フオトレジ
ストと共に、除去することにより形成されている
ことを特徴とする実用新案登録請求の範囲第１項
記載の薄膜トランジスタ。[Claims for Utility Model Registration] (1) A silicon compound is applied to a substrate on which a gate electrode is formed and a portion of the substrate surface other than the portion where the gate electrode is formed, and then the gate electrode is formed by baking. A planarizing insulating film formed to have a thickness substantially equal to the film thickness, a gate insulating film formed at least on the gate electrode surface, a semiconductor film sequentially formed on the gate insulating film, and a source and drain electrode. A thin film transistor characterized by comprising: (2) A utility model characterized in that the flattening insulating film is formed by coating a silicon compound on the substrate and the gate electrode, baking it, and then etching it to the extent that the surface of the gate electrode is exposed. A thin film transistor according to claim 1. (3) The planarizing insulating film is formed by applying a silicon compound solution onto the substrate and the gate electrode covered with the photoresist to form a film, and then removing the film together with the photoresist. A thin film transistor according to claim 1 of the utility model registration claim, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11427787U JPS6418757U (en) | 1987-07-25 | 1987-07-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11427787U JPS6418757U (en) | 1987-07-25 | 1987-07-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6418757U true JPS6418757U (en) | 1989-01-30 |
Family
ID=31354874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11427787U Pending JPS6418757U (en) | 1987-07-25 | 1987-07-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6418757U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529347A (en) * | 1990-10-12 | 1993-02-05 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method therefor |
| US8064003B2 (en) | 2003-11-28 | 2011-11-22 | Tadahiro Ohmi | Thin film transistor integrated circuit device, active matrix display device, and manufacturing methods of the same |
-
1987
- 1987-07-25 JP JP11427787U patent/JPS6418757U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529347A (en) * | 1990-10-12 | 1993-02-05 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method therefor |
| US8064003B2 (en) | 2003-11-28 | 2011-11-22 | Tadahiro Ohmi | Thin film transistor integrated circuit device, active matrix display device, and manufacturing methods of the same |
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