JPS6413856U - - Google Patents
Info
- Publication number
- JPS6413856U JPS6413856U JP6175087U JP6175087U JPS6413856U JP S6413856 U JPS6413856 U JP S6413856U JP 6175087 U JP6175087 U JP 6175087U JP 6175087 U JP6175087 U JP 6175087U JP S6413856 U JPS6413856 U JP S6413856U
- Authority
- JP
- Japan
- Prior art keywords
- vertical synchronization
- field
- field determination
- determination circuit
- end time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は本考案の一実施例であるフイールド判
定回路１の電気的構成を示すブロツク図、第２図
はフイールド判定回路１の動作を説明するための
タイミングチヤート、第３図および第４図は典型
的な先行技術のフイールド判定回路の動作を説明
するためのタイミングチヤートである。
１……フイールド判定回路、２，３……単安定
マルチバイブレータ、４〜８……Ｄ型フリツプフ
ロツプ、１１……インバータ、１２……ＮＡＮＤ
回路、Ａ……同期信号、ＶＢ……垂直帰線期間、
ＴＳ……垂直同期パルス期間、Ｐ……等化パルス
、ＴＦ……前期等化パルス期間、ＴＢ……後期等
化パルス期間。
FIG. 1 is a block diagram showing the electrical configuration of a field determination circuit 1 which is an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the field determination circuit 1, and FIGS. 3 and 4 is a timing chart illustrating the operation of a typical prior art field determination circuit. 1... Field determination circuit, 2, 3... Monostable multivibrator, 4-8... D-type flip-flop, 11... Inverter, 12... NAND
Circuit, A...Synchronization signal, VB...Vertical retrace period,
TS...Vertical synchronization pulse period, P...Equalization pulse, TF...Early equalization pulse period, TB...Late equalization pulse period.
Claims (1)
イールドであるかを判定するフイールド判定回路
において、 垂直同期パルスが配置される垂直同期信号の開
始時刻と終了時刻とを検出する検出手段と、 前記検出手段からの前記終了時刻に対応する信
号によつて垂直同期期間の時間的に後続して配置
された等化パルスを計数して演算する演算手段と
を含み、 前記演算手段に基づいてフイールド判定を行な
うことを特徴とするフイールド判定回路。[Claim for Utility Model Registration] In a field determination circuit that determines whether an input video signal is an odd field or an even field, the start time and end time of a vertical synchronization signal in which a vertical synchronization pulse is arranged are detected. a detecting means; and a calculating means for counting and calculating equalization pulses arranged temporally subsequent to the vertical synchronization period using a signal corresponding to the end time from the detecting means, the calculating means A field determination circuit is characterized in that it performs field determination based on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6175087U JPS6413856U (en) | 1987-04-22 | 1987-04-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6175087U JPS6413856U (en) | 1987-04-22 | 1987-04-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6413856U true JPS6413856U (en) | 1989-01-24 |
Family
ID=31287395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6175087U Pending JPS6413856U (en) | 1987-04-22 | 1987-04-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6413856U (en) |
-
1987
- 1987-04-22 JP JP6175087U patent/JPS6413856U/ja active Pending
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