JPS6412718A - Double pulse generation circuit - Google Patents

Double pulse generation circuit

Info

Publication number
JPS6412718A
JPS6412718A JP62169288A JP16928887A JPS6412718A JP S6412718 A JPS6412718 A JP S6412718A JP 62169288 A JP62169288 A JP 62169288A JP 16928887 A JP16928887 A JP 16928887A JP S6412718 A JPS6412718 A JP S6412718A
Authority
JP
Japan
Prior art keywords
coaxial cable
whose
dly
transistor
double pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62169288A
Other languages
Japanese (ja)
Other versions
JPH0756934B2 (en
Inventor
Shusaku Shimada
Hiroshi Kawarabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP62169288A priority Critical patent/JPH0756934B2/en
Publication of JPS6412718A publication Critical patent/JPS6412718A/en
Publication of JPH0756934B2 publication Critical patent/JPH0756934B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent skew from being generated and to generate a stable double pulse, by connecting a coaxial cable whose one side is opened, and setting a delay time from the output terminal of a buffer gate as an interval time. CONSTITUTION:To the connecting line of the collector electrode of a transistor Q and the buffer gate U2, the one end of the coaxial cable DLY whose one end is opened is connected, and a positive voltage source +V is connected via a resistor R4. The delay time of the coaxial cable DLY is adjusted to the delay time of 1/2 of the interval time T. When a pulse Vin is applied, it is added on the transistor Q as a voltage V1. By turning on the transistor Q, a signal is reciprocated in the coaxial cable DLY whose one end is opened as shown in path B. As a result, the double pulse whose interval time is T1 can be taken out from the output terminal OUT of the buffer gate U2.
JP62169288A 1987-07-07 1987-07-07 Double pulse generation circuit Expired - Lifetime JPH0756934B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62169288A JPH0756934B2 (en) 1987-07-07 1987-07-07 Double pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62169288A JPH0756934B2 (en) 1987-07-07 1987-07-07 Double pulse generation circuit

Publications (2)

Publication Number Publication Date
JPS6412718A true JPS6412718A (en) 1989-01-17
JPH0756934B2 JPH0756934B2 (en) 1995-06-14

Family

ID=15883740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62169288A Expired - Lifetime JPH0756934B2 (en) 1987-07-07 1987-07-07 Double pulse generation circuit

Country Status (1)

Country Link
JP (1) JPH0756934B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03207336A (en) * 1990-01-10 1991-09-10 Olympus Optical Co Ltd Externally attached television camera for endoscope
CN100417983C (en) * 2004-06-03 2008-09-10 夏普株式会社 Liquid crystal display device and substrate to be used for liquid crystal display device, and methods for producing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854725A (en) * 1981-09-29 1983-03-31 Fujitsu Ltd Delay circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854725A (en) * 1981-09-29 1983-03-31 Fujitsu Ltd Delay circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03207336A (en) * 1990-01-10 1991-09-10 Olympus Optical Co Ltd Externally attached television camera for endoscope
CN100417983C (en) * 2004-06-03 2008-09-10 夏普株式会社 Liquid crystal display device and substrate to be used for liquid crystal display device, and methods for producing the same

Also Published As

Publication number Publication date
JPH0756934B2 (en) 1995-06-14

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